MAX11101 Datasheet, PDF (9/19 Pages) Maxim Integrated Products – 14-Bit, +5V, 200ksps ADC with 10μA Shutdown

MAX11101
14-Bit, +5V, 200ksps ADC with 10µA Shutdown
VDD
1mA
DOUT
DOUT
1mA
C_LOAD = 50pF
CLOAD = 50pF
DGND
DGND
a) V_OL TO V_OH
b) HIGH-Z TO VOL AND VOH TO VOL
Figure 1. Load Circuits for DOUT Enable Time and SCLK to
DOUT Delay Time
VDD
1mA
DOUT
DOUT
1mA
C_LOAD = 50pF
CLOAD = 50pF
DGND
DGND
a) V_OH TO HIGH-Z
b) VOL TO HIGH-Z
Figure 2. Load Circuits for DOUT Disable Time
Detailed Description
The MAX11101 includes an input track-and-hold (T/H)
and successive-approximation register (SAR) circuitry to
convert an analog input signal to a digital 14-bit output.
Figure 4 shows the MAX11101 in its simplest configura-
tion. The serial interface requires only three digital lines
(SCLK, CS, and DOUT) and provides an easy interface
to microprocessors (FPs).
The MAX11101 has two power modes: normal and shut-
down. Driving CS high places the MAX11101 in shut-
down, reducing the supply current to 0.1FA (typ), while
pulling CS low places the MAX11101 in normal operating
mode. Falling edges on CS initiate conversions that are
driven by SCLK. The conversion result is available at
DOUT in unipolar serial format. The serial data stream
consists of eight zeros followed by the data bits (MSB
first). Figure 3 shows the interface-timing diagram.
Analog Input
Figure 5 illustrates the input sampling architecture of the
ADC. The voltage applied at REF sets the full-scale input
voltage.
Track-and-Hold (T/H)
In track mode, the analog signal is acquired on the inter-
nal hold capacitor. In hold mode, the T/H switches open
and the capacitive DAC samples the analog input.
CS
SCLK
tCSS
tCL
tCH
tCP
tCSW
tCSH
tDO
tDV
t_TR
DOUT
Figure 3. Detailed Serial Interface Timing
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