MAX11101 Datasheet, PDF (10/19 Pages) Maxim Integrated Products – 14-Bit, +5V, 200ksps ADC with 10μA Shutdown

MAX11101
14-Bit, +5V, 200ksps ADC with 10µA Shutdown
AIN
AIN
CS
SCLK
V_REF
REF
DOUT
4.7µF
+5V
AVDD ^MAX11101
0.1µF
+5V
DVDD
AGND
0.1µF
DGND
CS
SCLK
DOUT
GND
Figure 4. Typical Operating Circuit
AIN
CSWITCH
3pF
TRACK
REF
CAPACITIVE DAC
HOLD
GND
CDAC 32pF
HOLD
ZERO
R_IN
800Ω
TRACK
AUTOZERO
RAIL
Figure 5. Equivalent Input Circuit
During the acquisition, the analog input (AIN) charges
capacitor CDAC. The acquisition interval ends on the
falling edge of the sixth clock cycle (Figure 6). At this
instant, the T/H switches open. The retained charge on
CDAC represents a sample of the input.
In hold mode, the capacitive digital-to-analog converter
(DAC) adjusts during the remainder of the conversion
cycle to restore node ZERO to zero within the limits of
14-bit resolution. At the end of the conversion, force CS
high and then low to reset the input side of the CDAC
switches back to AIN, and charge CDAC to the input
signal again.
The time required for the T/H to acquire an input signal is
a function of how quickly its input capacitance is charged.
If the input signal’s source impedance is high, the acqui-
sition time lengthens and more time must be allowed
between conversions. The acquisition time (t_ACQ) is the
maximum time the device takes to acquire the signal. Use
the following formula to calculate acquisition time:
t_ACQ = 11(R_S + R_IN) x 35pF
where R_IN = 800I, R_S = the input signal’s source
impedance, and t_ACQ is never less than 1.1Fs. A source
impedance less than 1kI does not significantly affect the
ADC’s performance.
To improve the input signal bandwidth under AC condi-
tions, drive AIN with a wideband buffer (> 4MHz) that
can drive the ADC’s input capacitance and settle quickly.
Input Bandwidth
The ADC’s input tracking circuitry has a 4MHz small-
signal bandwidth, so it is possible to digitize high-speed
transient events and measure periodic signals with
bandwidths exceeding the ADC’s sampling rate by using
undersampling techniques. To avoid aliasing of unwant-
ed high-frequency signals into the frequency band of
interest, use anti-alias filtering.
Analog Input Protection
Internal protection diodes, which clamp the analog input to
AVDD and/or AGND, allow the input to swing from V_AGND -
0.3V to V_AVDD + 0.3V, without damaging the device.
If the analog input exceeds 300mV beyond the supplies,
limit the input current to 10mA.
Digital Interface
Initialization After Power-Up
and Starting a Conversion
The digital interface consists of two inputs, SCLK and
CS, and one output, DOUT. A logic-high on CS places
the MAX11101 in shutdown (autoshutdown) and places
DOUT in a high-impedance state. A logic-low on CS
places the MAX11101 in the fully powered mode.
To start a conversion, pull CS low. A falling edge on CS
initiates an acquisition. SCLK drives the A/D conversion
and shifts out the conversion results (MSB first) at DOUT.
Timing and Control
Conversion-start and data-read operations are con-
trolled by the CS and SCLK digital inputs (Figure 6
and Figure 7). Ensure that the duty cycle on SCLK is
between 40% and 60% at 4.8MHz (the maximum clock
frequency). For lower clock frequencies, ensure that
the minimum high and low times are at least 65ns.
Conversions with SCLK rates less than 100kHz may
result in reduced accuracy due to leakage.
Note: Coupling between SCLK and the analog inputs
(AIN and REF) may result in an offset. Variations in
frequency, duty cycle, or other aspects of the clock
signal’s shape result in changing offset.
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