MAX11101 Datasheet, PDF (4/19 Pages) Maxim Integrated Products – 14-Bit, +5V, 200ksps ADC with 10μA Shutdown

MAX11101
14-Bit, +5V, 200ksps ADC with 10µA Shutdown
TIMING CHARACTERISTICS
(V_AVDD = V_DVDD = 4.75V to 5.25V, f_SCLK = 4.8MHz (50% duty cycle), 24 clocks/conversion (200ksps), V_REF = 4.096V, T_A = T_MIN to
T_MAX, unless otherwise noted. Typical values are at T_A = +25°C.) (See Figure 1, Figure 2, Figure 3, and Figure 6.)
PARAMETER
Acquisition Time
SCLK to DOUT Valid
CS Fall to DOUT Enable
CS Rise to DOUT Disable
CS Pulse Width
CS Fall to SCLK Rise Setup
CS Rise to SCLK Rise Hold
SCLK High Pulse Width
SCLK Low Pulse Width
SCLK Period
SYMBOL
t_ACQ
t_DO
t_DV
t_TR
t_CSW
t_CSS
t_CSH
t_CH
t_CL
t_CP
CONDITIONS
C_DOUT = 50pF
C_DOUT = 50pF
C_DOUT = 50pF
MIN TYP MAX UNITS
1.1
Fs
50
ns
80
ns
80
ns
50
ns
100
ns
0
ns
65
ns
65
ns
208
ns
TIMING CHARACTERISTICS
(V_AVDD = 4.75V to 5.25V, V_DVDD = 2.7V to 5.25V, f_SCLK = 4.8MHz (50% duty cycle), 24 clocks/conversion (200ksps), V_REF = +4.096V,
T_A = T_MIN to T_MAX, unless otherwise noted. Typical values are at T_A = +25°C.) (See Figure 1, Figure 2, Figure 3, and Figure 6.)
PARAMETER
Acquisition Time
SCLK to DOUT Valid
CS Fall to DOUT Enable
CS Rise to DOUT Disable
CS Pulse Width
CS Fall to SCLK Rise Setup
CS Rise to SCLK Rise Hold
SCLK High Pulse Width
SCLK Low Pulse Width
SCLK Period
SYMBOL
t_ACQ
t_DO
t_DV
t_TR
t_CSW
t_CSS
t_CSH
t_CH
t_CL
t_CP
CONDITIONS
C_DOUT = 50pF
C_DOUT = 50pF
C_DOUT = 50pF
MIN TYP MAX UNITS
1.1
Fs
100
ns
100
ns
80
ns
50
ns
100
ns
0
ns
65
ns
65
ns
208
ns
Note 2: V_AVDD = V_DVDD = +5V.
Note 3: Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range has
been calibrated.
Note 4: Offset and reference errors nulled.
Note 5: Conversion time is defined as the number of clock cycles multiplied by the clock period; clock has 50% duty cycle.
Note 6: Defined as the change in positive full scale caused by a Q5% variation in the nominal supply voltage.
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