MAX11101 Datasheet, PDF(12/19 Page) Maxim Integrated Products – 14-Bit, +5V, 200ksps ADC with 10μA Shutdown

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MAX11101

14-Bit, +5V, 200ksps ADC with 10ÂµA Shutdown

Output Coding and Transfer Function

The data output from the MAX11101 is binary and Figure 8

depicts the nominal transfer function. Code transitions

occur halfway between successive-integer LSB values

(VREF = 4.096V and 1 LSB = 250FV or 4.096V/16384).

Applications Information

External Reference

The MAX11101 requires an external reference with a volt-

age range between 3.8V and AVDD. Connect the exter-

nal reference directly to REF. Bypass REF to AGND with

a 4.7FF capacitor. When not using a low-ESR bypass

capacitor, use a 0.1FF ceramic capacitor in parallel with

the 4.7FF capacitor. Noise on the reference degrades

conversion accuracy.

The input impedance at REF is 40I for DC currents.

During a conversion, the external reference at REF must

deliver 100FA of DC load current and have an output

impedance of 10I or less.

For optimal performance, buffer the reference through

an op amp and bypass the REF input. Consider the

MAX11101âs equivalent input noise (80FVRMS) when

choosing a reference.

OUTPUT CODE

11 . . . 111

11 . . . 110

11 . . . 101

FULL-SCALE

TRANSITION

00 . . . 011

00 . . . 010

00 . . . 001

00 . . . 000

012 3

INPUT VOLTAGE (LSB)

FS = VREF

1LSB = VREF

16384

FS - 3/2 LSB

Figure 8. Unipolar Transfer Function, Full Scale (FS) = VREF,

Zero Scale (ZS) = GND

Input Buffer

Most applications require an input buffer amplifier to

achieve 14-bit accuracy. If the input signal is multi-

plexed, switch the input channel immediately after acqui-

sition, rather than near the end of or after a conversion

(Figure 9). This allows the maximum time for the input

buffer amplifier to respond to a large step change in the

input signal. The input amplifier must have a slew rate of

at least 2V/Fs to complete the required output voltage

change before the beginning of the acquisition time.

At the beginning of the acquisition, the internal sampling

capacitor array connects to AIN (the amplifier output),

causing some output disturbance. Ensure that the sampled

voltage has settled before the end of the acquisition time.

Digital Noise

Digital noise can couple to AIN and REF. The conversion

clock (SCLK) and other digital signals active during input

acquisition contribute noise to the conversion result. Noise

signals synchronous with the sampling interval result in

an effective input offset. Asynchronous signals produce

random noise on the input, whose high-frequency compo-

nents may be aliased into the frequency band of interest.

Minimize noise by presenting a low impedance (at the

frequencies contained in the noise signal) at the inputs.

This requires bypassing AIN to AGND, or buffering the

input with an amplifier that has a small-signal bandwidth

of several MHz, or preferably both. AIN has about 4MHz

of bandwidth.

Distortion

Avoid degrading dynamic performance by choosing an

amplifier with distortion much less than the MAX11101âs

total harmonic distortion (THD = -99dB at 1kHz) at

frequencies of interest. If the chosen amplifier has

insufficient common-mode rejection, which results in

degraded THD performance, use the inverting configu-

ration (positive input grounded) to eliminate errors from

this source. Low temperature-coefficient, gain-setting

resistors reduce linearity errors caused by resistance

changes due to self-heating. To reduce linearity errors

due to finite amplifier gain, use amplifier circuits with suf-

ficient loop gain at the frequencies of interest.

DC Accuracy

To improve DC accuracy, choose a buffer with an offset

much less than the MAX11101âs offset (1mV (max) for

+5V supply), or whose offset can be trimmed while main-

taining stability over the required temperature range.

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