MAX11101 Datasheet, PDF (13/19 Pages) Maxim Integrated Products – 14-Bit, +5V, 200ksps ADC with 10μA Shutdown

MAX11101
14-Bit, +5V, 200ksps ADC with 10µA Shutdown
A0 A1
IN1
IN2 _4-TO-1
MUX
IN3
OUT
IN4
MAX11101
AIN
CS
CLK
CONVERSION
ACQUISITION
CS
A0
A1
CHANGE MUX INPUT HERE
Figure 9. Change Multiplexer Input Near Beginning of Conversion to Allow Time for Slewing and Settling
Serial Interfaces
The MAX11101’s interface is fully compatible with SPI,
QSPI, and MICROWIRE standard serial interfaces.
If a serial interface is available, establish the CPU’s
serial interface as master, so that the CPU generates the
serial clock for the MAX11101. Select a clock frequency
between 100kHz and 4.8MHz:
1) Use a general-purpose I/O line on the CPU to pull CS
low.
2) Activate SCLK for a minimum of 24 clock cycles. The
serial data stream of eight leading zeros followed by
the MSB of the conversion result begins at the fall-
ing edge of CS. DOUT transitions on SCLK’s falling
edge and the output is available in MSB-first format.
Observe the SCLK to DOUT valid timing characteris-
tic. Clock data into the FP on SCLK’s rising edge.
3) Pull CS high at or after the 24th falling clock edge. If
CS remains low, trailing zeros are clocked out after
the 2 sub-bits, S1 and S0.
4) With CS high, wait at least 50ns (t_CSW) before starting a
new conversion by pulling CS low. A conversion can be
aborted by pulling CS high before the conversion ends.
Wait at least 50ns before starting a new conversion.
Data can be output in three 8-bit sequences or continu-
ously. The bytes contain the results of the conversion pad-
ded with eight leading zeros before the MSB. If the serial
clock has not been idled after the sub-bits (S1 and S0) and
CS has been kept low, DOUT sends trailing zeros.
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