MAX11101 Datasheet, PDF (16/19 Pages) Maxim Integrated Products – 14-Bit, +5V, 200ksps ADC with 10μA Shutdown

MAX11101
14-Bit, +5V, 200ksps ADC with 10µA Shutdown
SCLK
CS
1ST BYTE READ
2ND BYTE READ
12
16
DOUT*
0
0
0
0
0
*WHEN CS IS HIGH, DOUT = HIGH-Z
0
0
0
D13 D12 D11 D10 D9 D8 D7
MSB
D6 D5
3RD BYTE READ
20
24
D5 D4 D3 D2 D1 D0 S1 S0
LSB
HIGH-Z
Figure 12b. SPI Interface Timing with PIC16/PIC17 in Master Mode (CKE = 1, CKP = 0, SMP = 0, SSPM3 - SSPM0 =0001)
Table 1. Detailed SSPCON Register Contents
CONTROL BIT
WCOL
SSPOV
BIT 7
BIT 6
SSPEN BIT 5
CKP
SSPM3
SSPM2
SSPM1
SSPM0
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
MAX11101
SETTINGS
SYNCHRONOUS SERIAL-PORT CONTROL REGISTER (SSPCON)
X
Write Collision Detection Bit
X
Receive Overflow Detect Bit
Synchronous Serial-Port Enable Bit:
1
0: Disables serial port and configures these pins as I/O port pins.
1: Enables serial port and configures SCK, SDO, and SCI pins as serial port pins.
0
Clock Polarity Select Bit. CKP = 0 for SPI master mode selection.
0
0
0
Synchronous Serial-Port Mode Select Bit. Sets SPI master mode and selects f_CLK = f_OSC/16
1
Table 2. Detailed SSPSTAT Register Contents
CONTROL BIT
SMP
CKE
D/A
P
S
R/W
UA
BF
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
MAX11101
SETTINGS
SYNCHRONOUS SERIAL-PORT CONTROL REGISTER (SSPSTAT)
0
SPI Data Input Sample Phase. Input data is sampled at the middle of the data output time.
1
SPI Clock Edge Select Bit. Data will be transmitted on the rising edge of the serial clock.
X
Data Address Bit
X
STOP Bit
X
START Bit
X
Read/Write Bit Information
X
Update Address
X
Buffer Full Status Bit
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