DS1558 Datasheet, PDF (9/18 Pages) Dallas Semiconductor – Watchdog Clock with NV RAM Control

DS1558
Table 3. ALARM MASK BITS
AM4
1
1
1
1
0
AM3
1
1
1
0
0
AM2
1
1
0
0
0
AM1
1
0
0
0
0
ALARM RATE
Once per second
When seconds match
When minutes and seconds match
When hours, minutes, and seconds match
When date, hours, minutes, and seconds match
When the RTC register values match alarm register settings, AF is set to a 1. If AE is also set to a 1, the
alarm condition activates the IRQ /FT pin. The IRQ /FT signal is cleared by a read or write to the flags
register (address 7FFF0h). When CE is active, the IRQ /FT signal can be cleared by having the address
stable for as short as 15ns and either OE or WE active, but is not guaranteed to be cleared unless t_RC is
fulfilled (Figure 2). Once the address has been selected for at least 15ns, the IRQ /FT signal can be cleared
immediately, but is not guaranteed to be cleared until t_RC is fulfilled (Figure 3). The alarm flag is also
cleared by a read or write to the flags register, but the flag does not change states until the end of the
read/write cycle and the IRQ /FT signal has been cleared.
The IRQ /FT pin can also be activated in the battery-backed mode. The IRQ /FT goes low if an alarm
occurs and both ABE and AE are set. The ABE and AE bits are cleared during the power-up transition,
but an alarm generated during power-up sets AF. Therefore, the AF bit can be read after system power-up
to determine if an alarm was generated during the power-up sequence. Figure 4 illustrates alarm timing
during the backup-battery mode and power-up states.
Figure 2. CLEARING IRQ WAVEFORMS ACTIVE
Figure 3. CLEARING IRQ WAVEFORMS
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