DS1558 Datasheet, PDF (5/18 Pages) Dallas Semiconductor – Watchdog Clock with NV RAM Control

Figure 1. BLOCK DIAGRAM
DS1558
NOTE: ANY UNUSED UPPER ADDRESS PINS MUST BE CONNECTED TO VCC TO PROPERLY ADDRESS THE RTC.
Table 1. OPERATING MODES
V_CC
V_CC > V_PF
CE OE WE DQ0–DQ7
V_IH X X
V_IL X V_IL
V_IL V_IL V_IH
V_IL V_IH V_IH
High-Z
D_IN
D_OUT
High-Z
V_SO < V_CC < V_PF X X X High-Z
V_CC < V_SO < V_PF X X X High-Z
MODE
Deselect
Write
Read
Read
Deselect
Data Retention
POWER
Standby
Active
Active
Active
CMOS Standby
Battery Current
DATA READ MODE
The DS1558 is in the read mode whenever CE is low and WE is high. The device architecture allows
ripple-through access to any valid address location. Valid data is available at the DQ pins within t_AA after
the last address input is stable, provided that CE and OE access times are satisfied. If CE or OE access
times are not met, valid data is available at the latter of chip-enable access (t_CEA) or at output-enable
access time (t_OEA). The state of the data input/output pins (DQ) is controlled by CE and OE . If the
outputs are activated before t_AA, the data lines are driven to an intermediate state until t_AA. If the address
inputs are changed while CE and OE remain valid, output data remains valid for output-data hold time
(tOH), but then goes indeterminate until the next address access.
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