DS1558 Datasheet, PDF (8/18 Pages) Dallas Semiconductor – Watchdog Clock with NV RAM Control

DS1558
READING THE CLOCK
When reading the RTC data, it is recommended to halt updates to the external set of double-buffered
RTC registers. This puts the external registers into a static state, allowing data to be read without register
values changing during the read process. Normal updates to the internal registers continue while in this
state. External updates are halted when a 1 is written into the read bit, B6 of the control register
(7FFF8h). As long as a 1 remains in the control register read bit, updating is halted. After a halt is issued,
the registers reflect the RTC count (day, date, and time) that was current at the moment the halt command
is issued. Normal updates to the external set of registers resume within 1 second after the read bit is set to
a 0 for a minimum of 500ms. The read bit must be a 0 for a minimum of 500ms to ensure the external
registers are updated.
SETTING THE CLOCK
The MSB bit, B7, of the control register is the write bit. Setting the write bit to a 1, like the read bit, halts
updates to the 7FFF8h–7FFFFh registers. After setting the write bit to a 1, RTC registers can be loaded
with the desired RTC count (day, date, and time) in 24-hour BCD format. Setting the write bit to a 0 then
transfers the values written to the internal RTC registers and allows normal operation to resume.
CLOCK ACCURACY
The accuracy of the clock is dependent upon the accuracy of the crystal and the accuracy of the match
between the capacitive load of the oscillator circuit and the capacitive load for which the crystal was
trimmed. Additional error is added by the crystal-frequency drift caused by temperature shifts. External
circuit noise coupled into the oscillator circuit can result in the clock running fast. Refer to Application
Note 58 “Crystal Considerations with Dallas Real-Time Clocks” for detailed information.
FREQUENCY TEST MODE
The DS1558 frequency test mode uses the open-drain IRQ /FT output. With the oscillator running, the
IRQ /FT output toggles at 512Hz when the FT bit is a 1, the alarm-flag enable bit (AE) is a 0, and the
watchdog-enable bit (WDS) is a 1, or the watchdog register is reset (register 7FFF7h = 00h). The IRQ /FT
output and the frequency test mode can be used as a measure of the actual frequency of the 32.768kHz
RTC oscillator. The IRQ /FT pin is an open-drain output that requires a pullup resistor for proper
operation. The FT bit is cleared to a 0 on power-up.
USING THE CLOCK ALARM
The alarm settings and control for the DS1558 reside within registers 7FFF2h–7FFF5h. Register 7FFF6h
contains two alarm-enable bits: alarm enable (AE) and alarm in backup enable (ABE). The AE and ABE
bits must be set as described below for the IRQ /FT output to be activated for a matched alarm condition.
The alarm can be programmed to activate on a specific day of the month or repeat every day, hour,
minute, or second. It can also be programmed to go off while the DS1558 is in the battery-backed state of
operation to serve as a system wake-up. Alarm mask bits AM1–AM4 control the alarm mode. Table 3
shows the possible settings. Configurations not listed in the table default to the once-per-second mode to
notify the user of an incorrect alarm setting.
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