DS1558 Datasheet, PDF (6/18 Pages) Dallas Semiconductor – Watchdog Clock with NV RAM Control

DS1558
DATA WRITE MODE
The DS1558 is in the write mode whenever WE and CE are in their active state. The start of a write is
referenced to the latter occurring transition of WE or CE . The addresses must be held valid throughout
the cycle. CE and WE must return inactive for a minimum of t_WR prior to the initiation of a subsequent
read or write cycle. Data in must be valid t_DS prior to the end of the write and remain valid for t_DH
afterward. In a typical application, the OE signal is high during a write cycle. However, OE can be active
provided that care is taken with the data bus to avoid bus contention. If OE is low prior to WE
transitioning low, the data bus can become active with read data defined by the address inputs. A low
transition on WE then disables the outputs t_WEZ after WE goes active.
DATA RETENTION MODE
The 5V device is fully accessible and data can be written and read only when V_CC is greater than V_PF.
However, when V_CC is below the power-fail point V_PF (point at which write protection occurs), the
internal clock registers and SRAM are blocked from any access. When V_CC falls below the battery switch
point V_SO (battery supply level), device power is switched from the V_CC pin to the backup battery. RTC
operation and SRAM data are maintained from the battery until V_CC is returned to nominal levels.
The 3.3V device is fully accessible and data can be written and read only when V_CC is greater than V_PF.
When V_CC falls below V_PF, access to the device is inhibited. If V_PF is less than V_SO, the device power is
switched from V_CC to the internal backup lithium battery when V_CC drops below V_PF. If V_PF is greater
than V_SO, the device power is switched from V_CC to the internal backup lithium battery when V_CC drops
below V_SO. RTC operation and SRAM data are maintained from the battery until V_CC is returned to
nominal levels.
All control, data, and address signals must be powered down when V_CC is powered down.
BATTERY LONGIVITY
The battery lifetime is dependent on the RAM battery standby current and the DS1558 internal clock
oscillator current. The total battery current is I_OSC + I_CCO. When V_CC is above V_PF, I_BAT current is less than
50nA. The DS1558 has an internal circuit to prevent battery charging. No external protection components
are required, and none should be used. The DS1558 has two battery pins that operate independently; the
DS1558 selects the higher of the two inputs. If only one battery is used, the battery should be attached to
V_BAT1, and V_BAT2 should be grounded.
INTERNAL BATTERY MONITOR
The DS1558 constantly monitors the battery voltage of the internal battery. The battery-low flag (BLF)
bit of the flags register (B4 of 7FFF0h) is not writable and should always be a 0 when read. If a 1 is ever
present, both battery inputs are below 1.8V and both the contents of the RTC and RAM are questionable.
POWER-ON RESET
A temperature-compensated comparator circuit monitors the level of V_CC. When V_CC falls to the power-
fail trip point, the RST signal (open drain) is pulled low. When V_CC returns to nominal levels, the RST
signal continues to be pulled low for a period of 40ms to 200ms. The power-on reset function is
independent of the RTC oscillator and thus is operational whether or not the oscillator is enabled.
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