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DS1558 Datasheet, PDF (4/18 Pages) Dallas Semiconductor – Watchdog Clock with NV RAM Control
DS1558
DESCRIPTION
The DS1558 is a full-function, year 2000-compliant (Y2KC), real-time clock/calendar with an RTC
alarm, watchdog timer, power-on reset, battery monitor, and NV SRAM controller. User access to all
registers within the DS1558 is accomplished with a byte-wide interface as shown in Figure 1. The RTC
registers contain century, year, month, date, day, hours, minutes, and seconds data in 24-hour BCD
format. Corrections for day of month and leap year are made automatically.
The DS1558 maps the RTC registers into the SRAM address space and constantly monitors A0–A18.
When any of the upper 16 address locations are accessed, the DS1558 inhibits CER and OER to the
SRAM, and redirects reads and writes to the RTC registers within the DS1558. The DS1558 can be used
with SRAMs up to 524,272 addresses. Smaller SRAMs can be used, provided that the unused upper
address lines on the DS1558 are connected to VCC.
The RTC registers are double-buffered into an internal and external set. The user has direct access to the
external set. Clock/calendar updates to the external set of registers can be disabled and enabled to allow
the user to access static data. Assuming the internal oscillator is turned on, the internal set of registers is
continuously updated; this occurs regardless of external register settings to guarantee that accurate RTC
information is always maintained.
The DS1558 has interrupt ( IRQ /FT) and reset ( RST ) outputs that can be used to control CPU activity.
The IRQ /FT interrupt output can be used to generate an external interrupt when the RTC register values
match user-programmed alarm values. The interrupt is always available while the device is powered from
the system supply, and it can be programmed to occur when in the battery-backed state to serve as a
system wake-up. The IRQ /FT output can also be used as a CPU watchdog timer. CPU activity is
monitored and an interrupt or reset output are activated if the correct activity is not detected within
programmed limits. The DS1558 power-on reset can be used to detect a system power-down or failure
and hold the CPU in a safe reset state until normal power returns and stabilizes; the RST output is used
for this function.
The DS1558 also contains its own power-fail circuitry, which automatically protects the data in the clock
and SRAM against out-of-tolerance VCCI conditions by inhibiting the CE input when the VCC supply
enters an out-of-tolerance condition. When VCCI goes below the level of VBAT, the external battery is
switched on to supply energy to the clock and the external SRAM. This feature provides a high degree of
data security during unpredictable system operation brought on by low VCC levels.
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