DS3100_09 Datasheet, PDF (87/227 Pages) Maxim Integrated Products – Stratum 2/3E/3 Timing Card IC

DS3100
Register Name:
Register Description:
Register Address:
MSR1
Master Status Register 1
05h
Name
Default
Bit 7
IC8
1
Bit 6
IC7
1
Bit 5
IC6
1
Bit 4
IC5
1
Bit 3
IC4
1
Bit 2
IC3
1
Bit 1
IC2
1
Bit 0
IC1
1
Bits 7 to 0: Input Clock Status Change (IC8 to IC1). Each of these latched status bits is set to 1 when the
corresponding VALSR1 status bit changes state (set or cleared). If soft frequency limit alarms are enabled
(MCR10:SOFTEN = 1), then each of these latched status bits is also set to 1 when the corresponding SOFT bit in
the ISR registers changes state (set or cleared). Each bit is cleared when written with a 1 and not set again until
either the VALSR1 bit or the SOFT bit changes state again. When one of these latched status bits is set it can
cause an interrupt request on the INTREQ pin if the corresponding interrupt enable bit is set in the IER1 register.
See Section 7.5 for input clock validation/invalidation criteria.
Register Name:
Register Description:
Register Address:
MSR2
Master Status Register 2
06h
Name
Default
Bit 7
STATE
0
Bit 6
SRFAIL
0
Bit 5
IC14
1
Bit 4
IC13
1
Bit 3
IC12
1
Bit 2
IC11
1
Bit 1
IC10
1
Bit 0
IC9
1
Bit 7: T0 DPLL State Change (STATE). This latched status bit is set to 1 when the operating state of the T0 DPLL
changes. STATE is cleared when written with a 1 and not set again until the operating state changes again. When
STATE is set it can cause an interrupt request on the INTREQ pin if the STATE interrupt enable bit is set in the
IER2 register. The current operating state can be read from the T0STATE field of the OPSTATE register. See
Section 7.7.1.
Bit 6: Selected Reference Failed (SRFAIL). This latched status bit is set to 1 when the selected reference to the
T0 DPLL fails (i.e., no clock edges in two UI). SRFAIL is cleared when written with a 1. When SRFAIL is set it can
cause an interrupt request on the INTREQ pin if the SRFAIL interrupt enable bit is set in the IER2 register. SRFAIL
is not set in free-run mode or holdover mode. See Section 7.5.3.
Bits 5 to 0: Input Clock Status Change (IC14 to IC9). Each of these latched status bits is set to 1 when the
corresponding VALSR status bit changes state (set or cleared). If soft frequency limit alarms are enabled
(MCR10:SOFTEN = 1), then each of these latched status bits is also set to 1 when the corresponding SOFT bit in
the ISR registers changes state (set or cleared). Each bit is cleared when written with a 1 and not set again until
either the VALSR2 bit or the SOFT bit changes state again. When one of these latched status bits is set it can
cause an interrupt request on the INTREQ pin if the corresponding interrupt enable bit is set in the IER2 register.
See Section 7.5 for input clock validation/invalidation criteria.
Register Name:
Register Description:
Register Address:
FREQ3
Frequency Register 3
07h
Name
Default
Bit 7
—
0
Bit 6
—
0
Bit 5
—
0
Bit 4
—
0
Bit 3
—
0
Bit 2
Bit 1
FREQ[18:16]
0
0
Bits 2 to 0: Current DPLL Frequency (FREQ[18:16]). See the FREQ1 register description.
Bit 0
0
19-4546; Rev 9; 5/09
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