DS3100_09 Datasheet, PDF (175/227 Pages) Maxim Integrated Products – Stratum 2/3E/3 Timing Card IC

DS3100
Register Name:
Register Description:
Register Address:
BRSR1
BITS Receive Status Register 1 (DS1 and E1)
33h
Name
Default
Bit 7
RAIC
0
Bit 6
AISC
0
Bit 5
LOSC
0
Bit 4
OOFC
0
Bit 3
RAI
0
Bit 2
AIS
0
Bit 1
LOS
0
Bit 0
OOF
0
See Table 7-16 (DS1) and Table 7-17 (E1) for set and clear criteria for RAI, AIS, LOS and OOF.
Bit 7: Remote Alarm Indication Clear (RAIC). This latched status bit is set to 1 when BRIR1:RAI changes state
from high to low. RAIC is cleared when written with a 1. When RAIC is set it can cause an interrupt request on the
INTREQ pin if the RAIC interrupt enable bit is set in the BRIER1 register.
Bit 6: Alarm Indication Signal Clear (AISC). This latched status bit is set to 1 when BRIR1:AIS changes state
from high to low. AISC is cleared when written with a 1. When AISC is set it can cause an interrupt request on the
INTREQ pin if the AISC interrupt enable bit is set in the BRIER1 register.
Bit 5: Loss of Signal Clear (LOSC). This latched status bit is set to 1 when BRIR1:LOS changes state from high
to low. LOSC is cleared when written with a 1. When LOSC is set it can cause an interrupt request on the INTREQ
pin if the LOSC interrupt enable bit is set in the BRIER1 register.
Bit 4: Out of Frame Clear (OOFC). This latched status bit is set to 1 when BRIR1:OOF changes state from high to
low. OOFC is cleared when written with a 1. When OOFC is set it can cause an interrupt request on the INTREQ
pin if the OOFC interrupt enable bit is set in the BRIER1 register.
Bit 3: Remote Alarm Indication (RAI). This latched status bit is set to 1 when BRIR1:RAI changes state from low
to high. RAI is cleared when written with a 1. When RAI is set it can cause an interrupt request on the INTREQ pin
if the RAI interrupt enable bit is set in the BRIER1 register.
Bit 2: Alarm Indication Signal (AIS). This latched status bit is set to 1 when BRIR1:AIS changes state from low to
high. AIS is cleared when written with a 1. When AIS is set it can cause an interrupt request on the INTREQ pin if
the AIS interrupt enable bit is set in the BRIER1 register.
Bit 1: Loss of Signal (LOS). This latched status bit is set to 1 when BRIR1:LOS changes state from low to high.
LOS is cleared when written with a 1. When LOS is set it can cause an interrupt request on the INTREQ pin if the
LOS interrupt enable bit is set in the BRIER1 register. See also the Receive Sensitivity paragraph in Section
7.10.4.1.6.
Bit 0: Out of Frame (OOF). This latched status bit is set to 1 when BRIR1:OOF changes state from low to high.
OOF is cleared when written with a 1. When OOF is set it can cause an interrupt request on the INTREQ pin if the
OOF interrupt enable bit is set in the BRIER1 register.
19-4546; Rev 9; 5/09
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