DS3100_09 Datasheet, PDF (125/227 Pages) Maxim Integrated Products – Stratum 2/3E/3 Timing Card IC

DS3100
Register Name:
Register Description:
Register Address:
OCR3
Output Configuration Register 3
62h
Name
Default
Bit 7
1
Bit 6
Bit 5
OFREQ6[3:0]
0
0
Bit 4
0
Bit 3
1
Bit 2
Bit 1
OFREQ5[3:0]
0
1
Bit 0
0
Bits 7 to 4: Output Frequency of OC6 (OFREQ6[3:0]). This field specifies the frequency of output clock output
OC6. The frequencies of the T0 APLL and T4 APLL are configured in the T0CR1 and T4CR1 registers. The
Digital1 and Digital2 frequencies are configured in the MCR7 register. See Section 7.8.2.3. Note that if the T4
DPLL is configured for 62.5MHz (T4CR1:T4FREQ = 1001) and the T4 APLL is configured to lock to the T4 DPLL
(T0CR1:T4APT0 = 0), then OFREQ6 = 1100 specifies T4 APLL frequency divided by 10 to give an output
frequency of 25MHz.
0000 = Output disabled (i.e., low)
0001 = 2kHz
0010 = 8kHz
0011 = T0 APLL frequency divided by 2
0100 = Digital1 (see Table 7-8)
0101 = T0 APLL frequency
0110 = T0 APLL frequency divided by 16
0111 = T0 APLL frequency divided by 12
1000 = T0 APLL frequency divided by 8
1001 = T0 APLL frequency divided by 6
1010 = T0 APLL frequency divided by 4
1011 = T4 APLL frequency divided by 64
1100 = T4 APLL frequency divided by 48 (or by 10, see note above)
1101 = T4 APLL frequency divided by 16
1110 = T4 APLL frequency divided by 8
1111 = T4 APLL frequency divided by 4
Bits 3 to 0: Output Frequency of OC5 (OFREQ5[3:0]). This field specifies the frequency of output clock OC5.
The frequencies of the T0 APLL and T4 APLL are configured in the T0CR1 and T4CR1 registers. The Digital1 and
Digital2 frequencies are configured in the MCR7 register. See Section 7.8.2.3. Note that if the T4 DPLL is
configured for 62.5MHz (T4CR1:T4FREQ = 1001) and the T4 APLL is configured to lock to the T4 DPLL
(T0CR1:T4APT0 = 0), then OFREQ5 = 1100 specifies T4 APLL frequency divided by 10 to give an output
frequency of 25MHz.
0000 = Output disabled (i.e., low)
0001 = 2kHz
0010 = 8kHz
0011 = Digital2 (see Table 7-8)
0100 = Digital1 (see Table 7-8)
0101 = T0 APLL frequency divided by 48
0110 = T0 APLL frequency divided by 16
0111 = T0 APLL frequency divided by 12
1000 = T0 APLL frequency divided by 8
1001 = T0 APLL frequency divided by 6
1010 = T0 APLL frequency divided by 4
1011 = T4 APLL frequency divided by 2
1100 = T4 APLL frequency divided by 48 (or by 10, see note above)
1101 = T4 APLL frequency divided by 16
1110 = T4 APLL frequency divided by 8
1111 = T4 APLL frequency divided by 4
19-4546; Rev 9; 5/09
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