DS3100_09 Datasheet, PDF (181/227 Pages) Maxim Integrated Products – Stratum 2/3E/3 Timing Card IC

DS3100
Register Name:
Register Description:
Register Address:
BTSR1
BITS Transmit Status Register 1 (DS1 and E1)
3Ah
Name
Default
Bit 7
—
0
Bit 6
—
0
Bit 5
—
0
Bit 4
—
0
Bit 3
TPDV/TAF
0
Bit 2
TMF
0
Bit 1
LOTCC
0
Bit 0
LOTC
0
Bit 3: Transmit Pulse Density Violation (TPDV) / Transmit Align Frame (TAF). In DS1 mode this latched status
bit functions as TPDV and is set to 1 when the transmit data stream does not meet the ANSI T1.403 requirements
for pulse density: no more than 15 consecutive zeros and at least N ones in each and every time window of 8 x (N
+1) bits where N = 1 through 23. In E1 mode this bit functions as TAF and is set to 1 every 250 μs at the beginning
of align frames. TPDV/TAF is cleared when written with a 1. When TPDV/TAF is set it can cause an interrupt to
occur on the INTREQ pin if the TPDV/TAF interrupt enable bit is set in the BTIER1 register. See Section 7.10.6.3.
Bit 2: Transmit Multi-Frame (TMF). In DS1 mode this latched status bit is set to 1 every 1.5 ms on superframe
boundaries (SF mode) or every 3 ms on extended superframe boundaries (ESF mode). In E1 mode this bit is set
every 2 ms on multiframe boundaries. TMF is cleared when written with a 1. When TMF is set it can cause an
interrupt to occur on the INTREQ pin if the TMF interrupt enable bit is set in the BTIER1 register. See Section
7.10.6.4.
Bit 1: Loss of Transmit Clock Clear (LOTCC). This latched status bit is set to 1 when the transmit clock source
has transitioned for approximately 15 MCLK periods. LOTCC is cleared when written with a 1. When LOTCC is set
it can cause an interrupt request on the INTREQ pin if the LOTCC interrupt enable bit is set in the BTIER1 register.
Bit 0: Loss of Transmit Clock (LOTC). This latched status bit is set to 1 when the transmit clock source has not
transitioned for approximately 15 MCLK periods. LOTC is cleared when written with a 1. When LOTC is set it can
cause an interrupt request on the INTREQ pin if the LOTC interrupt enable bit is set in the BTIER1 register.
Register Name:
Register Description:
Register Address:
BTIER1
BITS Transmit Interrupt Enable Register 1 (DS1 and E1)
3Bh
Name
Default
Bit 7
—
0
Bit 6
—
0
Bit 5
—
0
Bit 4
—
0
Bit 3
TPDV/TAF
0
Bit 2
TMF
0
Bit 1
LOTCC
0
Bit 0
LOTC
0
Bit 3: Interrupt Enable for Transmit Pulse Density Violation (TPDV) / Transmit Align Frame (TAF). This bit is
an interrupt enable for the TPDV/TMF bit in the BTSR1 register.
0 = Mask the interrupt
1 = Enable the interrupt
Bit 2: Interrupt Enable for Transmit Multi-Frame (TMF). This bit is an interrupt enable for the TMF bit in the
BTSR1 register.
0 = Mask the interrupt
1 = Enable the interrupt
Bit 1: Interrupt Enable for Loss of Transmit Clock Clear (LOTCC). This bit is an interrupt enable for the LOTCC
bit in the BTSR1 register.
0 = Mask the interrupt
1 = Enable the interrupt
Bit 0: Interrupt Enable for Loss of Transmit Clock (LOTC). This bit is an interrupt enable for the LOTC bit in the
BTSR1 register.
0 = Mask the interrupt
1 = Enable the interrupt
19-4546; Rev 9; 5/09
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