DS3100_09 Datasheet, PDF (18/227 Pages) Maxim Integrated Products – Stratum 2/3E/3 Timing Card IC

DS3100
Table 6-4. BITS Transmitter Pin Descriptions
PIN NAME⁽¹⁾ TYPE⁽²⁾
FUNCTION
L2
TCLK1
T12 TCLK2
Transmit Clock Output for BITS Transceiver 1. This pin presents the TCLK signal output
O₃
from the Tx Clock Mux block. This output is enabled/disabled by BCCR4:TCEN. The TSER1
pin is sampled on the TCLK1 edge specified by BCCR4:TCINV. See Section 7.10.3.
Transmit Clock Output for BITS Transceiver 2. This pin presents the TCLK signal output
O₃
from the Tx Clock Mux block. This output is enabled/disabled by BCCR4:TCEN. The TSER2
pin is sampled on the TCLK2 edge specified by BCCR4:TCINV. See Section 7.10.3.
M1 TOUT1
Transmit Multipurpose Output Pin for BITS Transceiver 1. This output is enabled/disabled
O₃
by BCCR4:TOEN. Its signal source is specified by BCCR4:TOUTS. Possible sources are the
DS1/E1 frame sync and the DS1/E1 multiframe sync. See Section 7.10.3.
P11 TOUT2
L1
TIN1
R12
TIN2
L3
TSER1
T13 TSER2
R3,
T3
R2,
T2
N15,
N16
P15,
P16
TTIP1
TRING1
TTIP2
TRING2
K3
THZE1
T14 THZE2
Transmit Multipurpose Output Pin for BITS Transceiver 2. This output is enabled/disabled
O₃
by BCCR4:TOEN. Its signal source is specified by BCCR4:TOUTS. Possible sources are the
DS1/E1 frame sync and the DS1/E1 multiframe sync. See Section 7.10.3.
Transmitter Multipurpose Input for BITS Transceiver 1. In most applications, the BITS
transmitter clock is sourced from one of output clocks OC1–OC7 or OC9, as specified by
I_PD
BCCR1:TCLKS. For special applications, TCLKS can be set to 0000 to the enable the
transmitter clock to be sourced from the TIN1 pin. Optionally TIN1 can source the frame or
multiframe sync in DS1 and E1 modes. In these latter cases, TIN1 is sampled on the TCLK1
edge specified by BCCR4:TCINV. See Section 7.10.3.
Transmitter Multipurpose Input for BITS Transceiver 2. In most applications, the BITS
transmitter clock is sourced from one of output clocks OC1-OC7 or OC9, as specified by
I_PD
BCCR1:TCLKS. For special applications, TCLKS can be set to 0000 to the enable the
transmitter clock to be sourced from the TIN2 pin. Optionally TIN2 can source the frame or
multiframe sync in DS1 and E1 modes. In these latter cases, TIN2 is sampled on the TCLK2
edge specified by BCCR4:TCINV. See Section 7.10.3.
Transmitter Serial Data Input for BITS Transceiver 1. When the BITS transmitter is in DS1
or E1 mode (i.e., when BMCR:TMODE = 0x), this pin is the source for the DS1/E1 data stream
I_PU
in NRZ format. TSER1 is sampled on the TCLK1 edge specified by BCCR4:TCINV. Payload
bits and optionally some overhead bits are sampled. Normally, this pin is wired high to achieve
an all-ones payload. This pin is ignored in other BITS transmitter modes and should be held
high or low. See Sections 7.10.5.2 and 7.10.6.2.
Transmitter Serial Data Input for BITS Transceiver 2. When the BITS transmitter is in DS1
or E1 mode (i.e., when BMCR:TMODE = 0x), this pin is the source for the DS1/E1 data stream
I_PU
in NRZ format. TSER2 is sampled on the TCLK2 edge specified by BCCR4:TCINV. Payload
bits and optionally some overhead bits are sampled. Normally, this pin is wired high to achieve
an all-ones payload. This pin is ignored in other BITS transmitter modes and should be held
high or low. See Sections 7.10.5.2 and 7.10.6.2.
Differential Transmitter Outputs for BITS Transceiver 1. These pins drive the outgoing
signal onto the transmit cable through a 1:2 step-up transformer. They can be placed in a
O_A
high-impedance state by pulling the THZE1 pin high or setting BLCR4:TE = 0 in BITS
transceiver 1. These pins are also high impedance when the transmitter is powered down
(BLCR4:TPD = 1). The two TTIP1 pins should be externally wired together, and the two
TRING1 pins should be externally wired together. See Section 7.10.4.
Differential Transmitter Outputs for BITS Transceiver 2. These pins drive the outgoing
signal onto the transmit cable through a 1:2 step-up transformer. They can be placed in a
O_A
high-impedance state by pulling the THZE2 pin high or setting BLCR4:TE = 0 in BITS
transceiver 2. These pins are also high impedance when the transmitter is powered down
(BLCR4:TPD = 1). The two TTIP2 pins should be externally wired together, and the two
TRING2 pins should be externally wired together. See Section 7.10.4.
Transmit High-Impedance Enable for BITS Transceiver 1. See Section 7.10.4.2.3.
I_PU
0 = TTIP1/TRING1 transmit data normally (must also have BLCR4:TE = 1 in BITS transceiver 1)
1 = TTIP1/TRING1 high impedance
Transmit High-Impedance Enable for BITS Transceiver 2. See Section 7.10.4.2.3.
I_PU
0 = TTIP2/TRING2 transmit data normally (must also have BLCR4:TE = 1 in BITS transceiver 2)
1 = TTIP2/TRING2 high impedance
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