MAX11800_1010 Datasheet, PDF (51/59 Pages) Maxim Integrated Products – Low-Power, Ultra-Small Resistive Touch-Screen Controllers with I2C/SPI Interface

Low-Power, Ultra-Small Resistive Touch-Screen
Controllers with I²C/SPI Interface
Measurement Averaging Configuration Register (0x03)*
BIT
NAME
DEFAULT
7
6
AVG_X[1:0]
0
0
5
4
AVG_Y[1:0]
0
0
3
2
AVG_Z1[1:0]
0
0
1
0
AVG_Z2[1:0]
0
0
BIT
NAME
DESCRIPTION
MAX11800/ MAX11802/
MAX11801 MAX11803
Averaging sample depth for X, Y, Z1, or Z2 measurements
7:6
AVG_X[1:0] If AVG_FLT = 0 (see the Operating Mode Configuration
Yes
Yes
Register (0x0B) section)
00: Single sample, no averaging
5:4
AVG_Y[1:0] ^{01: Take four samples, average two median samples}
10: Take eight samples, average four median samples
Yes
Yes
11: Take 16 samples, average eight median samples
If AVG_FLT = 1 (see the Operating Mode Configuration Register
3:2
AVG_Z1[1:0] _{(0x0B) section)}
Yes
Yes
00: Single sample, no averaging
01: Take four samples, average all samples
1:0
AVG_Z2[1:0] 10: Take eight samples, average all samples
Yes
Yes
11: Take 16 samples, average all samples
*The settings can be enabled and disabled through settings in the operating mode configuration register (0x0B), allowing for dynamic
configuration of averaging modes depending on operating mode.
ADC Sampling Time Configuration Register (0x04)*
BIT
NAME
DEFAULT
7
6
T_SAMPLE_X[1:0]
0
0
5
4
T_SAMPLE_Y[1:0]
0
0
3
2
T_SAMPLE_Z1[1:0]
0
0
1
0
T_SAMPLE_Z2[1:0]
0
0
BIT
NAME
DESCRIPTION
MAX11800/
MAX11801
MAX11802/
MAX11803
7:6
T_SAMPLE_X[1:0] Sampling time for X, Y, Z1 or Z2 measurements
Yes
Yes
5:4
T_SAMPLE_Y[1:0] ^{00: 4 x (2MHz oscillator clock period) = 2μs}
01: 16 x (2MHz oscillator clock period) = 8μs
3:2
T_SAMPLE_Z1[1:0] _{10: 64 x (2MHz oscillator clock period) = 32μs}
Yes
Yes
Yes
Yes
1:0
T_SAMPLE_Z2[1:0] 11: 256 x (2MHz oscillator clock period) = 128μs
Yes
Yes
*Time ADC spends sampling panel before starting conversion process. This time plus the ADC conversion time determines the sam-
pling rate within averaging operations. Be sure to allow adequate time to settle the ADC capacitors given the panel effective source
resistance.
______________________________________________________________________________________ 51