MAX11800_1010 Datasheet, PDF (40/59 Pages) Maxim Integrated Products – Low-Power, Ultra-Small Resistive Touch-Screen Controllers with I2C/SPI Interface

Low-Power, Ultra-Small Resistive Touch-Screen
Controllers with I²C/SPI Interface
CS
1
789
16 17
24 25
32
SCLK
DIN
A_i[6:0]
DOUT
D_i[7:0]
D_i+1[7:0]
Figure 20. SPI Multiple-Byte Register Read Sequence—MAX11800/MAX11802
D_i+2[7:0]
S
CS
SCLK
1
2
3
4
5
6
7
8
DIN
A6 A5 A4 A3 A2 A1 A0 W
Figure 21. SPI Conversion Command—MAX11800/MAX11802
SPI Conversion Command (MAX11800/MAX11802)
The sequence in Figures 20 and 21 shows the required
command format for issuing conversion requests. A
conversion request cannot be paired with multiple com-
mands or instructions. Any conversion command
issued while previous commands are being executed is
ignored.
I²C-Supported Sequence
(MAX11801/MAX11803)
The MAX11801/MAX11803 feature an I²C/SMBus™-
compatible, 2-wire serial interface consisting of a serial-
data line (SDA) and a serial-clock line (SCL). SDA and
SCL facilitate communication between the
MAX11801/MAX11803 and the master at clock rates up
to 400kHz. Figure 22 shows the 2-wire interface timing
diagram. The master generates SCL and initiates data
transfer on the bus.
The master device writes data to the MAX11801/
MAX11803 by transmitting the proper slave address fol-
lowed by the register address and then the data word.
Each transmit sequence is framed by a START (S) or
repeated START (Sr) condition and a STOP (P) condi-
tion. Each word transmitted to the MAX11801/
MAX11803 is 8 bits long and is followed by an acknowl-
edge clock pulse.
A master reading data from the MAX11801/MAX11803
transmits the proper slave address followed by a series
SMBus is a trademark of Intel Corp.
of nine SCL pulses. The MAX11801/MAX11803 trans-
mits data on SDA in sync with the master-generated
SCL pulses. The master acknowledges receipt of each
byte of data. Each read sequence is framed by a
START (S) or repeated START (Sr) condition, a not-
acknowledge, and a STOP (P) condition. SDA operates
as both an input and an open-drain output.
A pullup resistor, typically greater than 500Ω, is
required on SDA. SCL operates only as an input. A
pullup resistor, typically greater than 500Ω, is required
on SCL if there are multiple masters on the bus, or if the
single master has an open-drain SCL output. Series
resistors in line with SDA and SCL are optional. Series
resistors protect the digital inputs of the
MAX11801/MAX11803 from high-voltage spikes on the
bus lines and minimize crosstalk and undershoot of the
bus signals.
Bit Transfer
One data bit is transferred during each SCL cycle. The
data on SDA must remain stable during the high period
of the SCL pulse. Changes in SDA while SCL is high
are control signals (see the START and STOP
Conditions section).
START and STOP Conditions
SDA and SCL idle high when the bus is not in use. A
master initiates communication by issuing a START
condition. A START condition is a high-to-low transition
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