MAX11800_1010 Datasheet, PDF (38/59 Pages) Maxim Integrated Products – Low-Power, Ultra-Small Resistive Touch-Screen Controllers with I2C/SPI Interface

Low-Power, Ultra-Small Resistive Touch-Screen
Controllers with I²C/SPI Interface
SPI Communication Sequence
(MAX11800/MAX11802)
The SPI interface consists of three inputs, DIN, DCLK,
CS, and one output, DOUT. A logic-high on CS dis-
ables the MAX11800/MAX11802 digital interface and
places DOUT in a high-impedance state. Pulling CS low
enables the MAX11800/MAX11802 digital interface. The
MAX11800/MAX11802 provide two possible implemen-
tations of SPI instructions. In rising-edge-driven opera-
tions, the devices are able to run at maximum clock
speeds. Carefully consider the hold time requirements
of the MAX11800/MAX11802 and minimize board skew
contributions when running the MAX11800/MAX11802
at maximum clock speed. In falling-edge-driven opera-
tions, the device is less sensitive to board skew contri-
butions, but slower clock speeds are required to meet
the MAX11800/MAX11802 setup time requirements. For
the MAX11800/MAX11802, read patterns output data is
either latched on the rising edge running at maximum
clock rates or on the falling edges running at reduced
clock rates.
SPI Configuration Register Write
(MAX11800/MAX11802)
Figure 17 shows the supported write operation
sequence for the MAX11800/MAX11802. A single con-
figuration register can be written in a 2-byte operation,
composed of a target register address (A[6:0], plus a
write mode indicator bit) followed by data to be written
to the target register (D[7:0]).
During write sequences, the DOUT line is not accessed
by the SPI. DOUT remains high impedance throughout
the command. Using the optional bus holder, the DOUT
line retains the previous value unless altered by a
device sharing the bus.
The MAX11800/MAX11802 SPI interface supports multi-
ple register write operations within a single sequence
as shown in Figure 18. By repeating the address plus
data byte pairs (in write mode), an unlimited number of
registers can be written in a single transfer. Do not per-
mit to combine write and read operations within the
same SPI sequence.
CS
SCLK
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16
DIN
A6 A5 A4 A3 A2 A1 A0 W D7 D6 D5 D4 D3 D2 D1 D0
Figure 17. SPI Single Configuration Register Write Sequence—MAX11800/MAX11802
CS
1
SCLK
7
9
17
23 25
32
DIN
A_n [6:0]
D_n [7:0]
A_m [6:0]
Figure 18. SPI Multiple Configuration Register Write Sequence—MAX11800/MAX11802
D_m [7:0]
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