MAX11800_1010 Datasheet, PDF (39/59 Pages) Maxim Integrated Products – Low-Power, Ultra-Small Resistive Touch-Screen Controllers with I2C/SPI Interface

Low-Power, Ultra-Small Resistive Touch-Screen
Controllers with I²C/SPI Interface
SPI Configuration or
Result Register Read (MAX11800/MAX11802)
Figure 19 shows the read operation sequence for the
MAX11800/MAX11802. A single configuration register
can be read back in a 2-byte operation, composed of a
requested register address (A[6:0], plus a read mode
indicator bit) followed by the data contents from that reg-
ister (D[7:0]).
During read operations, the SPI takes control of the DOUT
line following the eight SCLK rising edge. The SPI retains
control of the DOUT line until CS rises, terminating the
operation. To support multiple register readback opera-
tions, data continues to be ported following the 16th rising
clock edge. For single-byte transfers, this sub-bit informa-
tion can be ignored, shown as S, in Figure 19.
The DOUT output on the MAX11800/MAX11802 includes
an optional bus holder to prevent the DOUT line from
maintaining an indeterminate state when vacated by the
device in the absence of an external bus pullup or bus
sharing devices. The bus holder is designed not to inter-
fere with other drivers sharing the DOUT line and holds
the last valid state of the line, regardless of source.
Disable the bus holder when not needed.
The MAX11800/MAX11802 support the combination of
the DIN and DOUT lines. To avoid data contention and
possible high current states, the master device must relin-
quish control of the combined line at the 8th clock rising
edge, allowing the MAX11800/MAX11802 to access the
line through the end of the sequence. This is terminated
on the rising edge of CS. See the SPI Timing
Characteristics for relevant details.
The MAX11800/MAX11802 also support multiple register
readback operations using a single command. The proto-
col requires the user to supply an initial starting register
location, followed by an unlimited number of clock pulses
for data readback.
The first data read back is from the start register. The
MAX11800/MAX11802 internal autoincrement counter
manages the data readback in later cycles. If autoin-
crement is supported, the next register location is read
back. If not, the last valid register location is read back
(see the Command and Register Map section for the
autoincrement attributes of each register). The following
example shows a valid sequence for the readback of
three register locations (D_i through D_i+2).
The autoincrement reads only the X, Y, Z1, Z2, and AUX
result registers preventing inadvertent readback of unre-
lated or reserved data locations. For example, if begin-
ning at the XMSB register, a user can cycle through the
XLSB register to the YMSB register and so forth up to the
AUXLSB register. The MAX11800/MAX11802 do not
autoincrement beyond the AUXLSB register. If clock
cycles continue to be given, the AUXLSB register read-
back is repeated.
The FIFO register does not autoincrement, which allows
multiple readbacks of the same location. This allows the
access of multiple FIFO memory blocks with a single read
operation. When reading back FIFO registers, data man-
agement is handled in blocks not bytes. As a result, when
an SPI read operation supplies at least one cycle of read-
back of the first byte of a FIFO block, the entire block is
marked as read, regardless of whether the block or even
byte readback is run to completion.
To illustrate, assume the MAX11800 is in autonomous
mode performing XY conversions and a FIFO readback
is requested starting at register 0x50. Clock cycles 9 to
40 are required to complete the readback of the first
available FIFO block_i = {XMSB_i, XLSB_i, YMSB_i, YLSB_i}
with the device updating in response to the 8th to 39th
clock rising edges. The host processor can complete
the readback data latching of YLSB_i[0] either on the
39th falling edge or the 40th rising edge. To support a
continued readback of further FIFO blocks, the device
updates the DOUT line to XMSB_i+1[7] in response to the
40th clock rising edge (though block_i+1 is not marked
as read). If the AP supplies a 42nd clock rising edge,
the FIFO block_i+1, if present, is marked as read, regard-
less of whether any further clock cycles are provided.
CS
SCLK
DIN
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16
A6 A5 A4 A3 A2 A1 A0 R
DOUT
D7 D6 D5 D4 D3 D2 D1 D0 S
Figure 19. SPI Single-Byte Register Read Sequence—MAX11800/MAX11802
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