MAX1519 Datasheet, PDF (5/43 Pages) Maxim Integrated Products – Dual-Phase, Quick-PWM Controllers for Programmable CPU Core Power Supplies

Dual-Phase, Quick-PWM Controllers for
Programmable CPU Core Power Supplies
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1, V+ = 15V, V_CC = V_DD = V_SHDN = V_TON = V_SKIP = V_S0 = V_S1 = V_CODE = 5V, V_FB = V_CMP = V_CMN = V_CSP = V_CSN
= 1.3V, OFS = SUS = GNDS = D0–D4 = GND; T_A = 0°C to +85°C, unless otherwise specified. Typical values are at T_A = +25°C.)
PARAMETER
GATE DRIVERS
DH_ Gate-Driver On-Resistance
DL_ Gate-Driver On-Resistance
SYMBOL
CONDITIONS
R_ON(DH)
R_ON(DL)
BST_ - LX_ forced to 5V
High state (pullup)
Low start (pulldown)
MIN TYP MAX UNITS
1.0
4.5
Ω
1.0
4.5
Ω
0.4
2
DH_ Gate-Driver Source/Sink
Current
I_DH
DH_ forced to 2.5V,
BST_ - LX_ forced to 5V
1.6
A
DL_ Gate-Driver Sink Current
I_DL(SINK) DL_ forced to 5V
DL_ Gate-Driver Source Current I_DL(SOURCE) DL_ forced to 2.5V
Dead Time
t_DEAD
DL_ rising
DH_ rising
VOLTAGE-POSITIONING AMPLIFIER
Input Offset Voltage
V_OS
Input Bias Current
I_BIAS
OAIN+, OAIN-
Op Amp Disable Threshold
V_OAIN-
4
A
1.6
A
35
ns
26
-1
+1
mV
0.1
200
nA
3
V_CC - 1
V_CC -
0.4
V
Common-Mode Input Voltage
Range
V_CM
Guaranteed by CMRR test
0
2.5
V
Common-Mode Rejection Ratio
Power-Supply Rejection Ratio
Large-Signal Voltage Gain
Output Voltage Swing
Input Capacitance
Gain-Bandwidth Product
Slew Rate
Capacitive-Load Stability
LOGIC AND I/O
SHDN Input High Voltage
SHDN Input Low Voltage
SHDN No-Fault Threshold
Three-Level Input Logic Levels
Logic Input Current
CMRR
PSRR
A_OA
V_OAIN+ = V_OAIN- = 0 to 2.5V
V_CC = 4.5V to 5.5V
R_L = 1kΩ to V_CC/2
|V_OAIN+ - V_OAIN-| ≥ 10mV, ^VCC ^{- V}FBH
R_L = 1kΩ to V_CC/2
V_FBL
No sustained oscillations
V_IH
V_IL
V_SHDN
SUS, SKIP
SHDN, SUS, SKIP
High
REF
Low
70
115
dB
75
100
dB
80
112
dB
77
300
mV
47
200
11
pF
3
MHz
0.3
V/µs
400
pF
0.8
V
0.4
V
12
15
V
2.7
1.2
2.3
V
0.8
-1
+1
µA
D0–D4 Logic Input High Voltage
1.6
V
D0–D4 Logic Input Low Voltage
0.8
V
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