MAX1519 Datasheet, PDF (30/43 Pages) Maxim Integrated Products – Dual-Phase, Quick-PWM Controllers for Programmable CPU Core Power Supplies

Dual-Phase, Quick-PWM Controllers for
Programmable CPU Core Power Supplies
the input voltage due to the typically low duty cycles.
The total load current at the PFM/PWM crossover
threshold (I_LOAD(SKIP)) is approximately:
I_LOAD(SKIP) =
η _TOTAL


V_OUTK
L




V_IN
- V_OUT
V_IN


where η_TOTAL is the number of active phases, and K is
the on-time scale factor (Table 6).
The switching waveforms may appear noisy and asyn-
chronous when light loading activates the pulse-skipping
operation, but this is a normal operating condition that
results in high light-load efficiency. Varying the inductor
value makes trade-offs between PFM noise and light-load
efficiency. Generally, low inductor values produce a
broader efficiency vs. load curve, while higher values
result in higher full-load efficiency (assuming that the coil
resistance remains fixed) and less output voltage ripple.
Penalties for using higher inductor values include larger
physical size and degraded load-transient response,
especially at low input voltage levels.
Current-Limit Circuit
The current-limit circuit employs a unique “valley” cur-
rent-sensing algorithm that uses current-sense resistors
between the current-sense inputs (C_P to C_N) as the
current-sensing elements. If the current-sense signal of
the selected phase is above the current-limit threshold,
the PWM controller does not initiate a new cycle
(Figure 8) until the inductor current of the selected
phase drops below the valley current-limit threshold.
When either phase trips the current limit, both phases
are effectively current limited since the interleaved con-
troller does not initiate a cycle with either phase.
Since only the valley current is actively limited, the actual
peak current is greater than the current-limit threshold by
an amount equal to the inductor ripple current. Therefore,
the exact current-limit characteristic and maximum load
capability are a function of the current-sense resistance,
inductor value, and battery voltage. When combined with
the undervoltage protection circuit, this current-limit
method is effective in almost every circumstance.
There is also a negative current limit that prevents
excessive reverse inductor currents when V_OUT is sink-
ing current. The negative current-limit threshold is set to
approximately 120% of the positive current limit, and
therefore tracks the positive current limit when ILIM is
adjusted. When a phase drops below the negative cur-
rent limit, the controller immediately activates an on-
time pulse—DL turns off, and DH turns on—allowing
the inductor current to remain above the negative cur-
rent threshold.
CBYP
VDD
DBST
BST
(RBST)*
CBST
DH
LX
VDD
DL
PGND
(CNL)*
INPUT
(VIN)
NH
L
NL
(RBST)* OPTIONAL—THE RESISTOR LOWERS EMI BY DECREASING THE SWITCHING
NODE RISE TIME.
(CNL)* OPTIONAL—THE CAPACITOR REDUCES LX TO DL CAPACITIVE COUPLING THAT
CAN CAUSE SHOOT-THROUGH CURRENTS.
Figure 9. Optional Gate-Driver Circuitry
The current-limit threshold is adjusted with an external
resistive voltage-divider at ILIM. The current-limit
threshold voltage adjustment range is from 10mV to
75mV. In the adjustable mode, the current-limit thresh-
old voltage is precisely 1/20 the voltage seen at ILIM.
The threshold defaults to 30mV when ILIM is connected
to V_CC. The logic threshold for switchover to the 30mV
default value is approximately V_CC - 1V.
Carefully observe the PC board layout guidelines to
ensure that noise and DC errors do not corrupt the cur-
rent-sense signals seen by the current-sense inputs
(C_P, C_N).
MOSFET Gate Drivers (DH, DL)
The DH and DL drivers are optimized for driving mod-
erately sized, high-side and larger, low-side power
MOSFETs. This is consistent with the low-duty factor
seen in the notebook CPU environment, where a large
V_IN - V_OUT differential exists. An adaptive dead-time
circuit monitors the DL output and prevents the high-
side FET from turning on until DL is fully off. There must
be a low-resistance, low-inductance path from the DL
driver to the MOSFET gate in order for the adaptive
dead-time circuit to work properly. Otherwise, the
sense circuitry in the Quick-PWM controller interprets
the MOSFET gate as “off” while there is actually charge
still left on the gate. Use very short, wide traces (50 mils
to 100 mils wide if the MOSFET is 1in from the device).
The dead time at the other edge (DH turning off) is
determined by a fixed 35ns internal delay.
The internal pulldown transistor that drives DL low is
robust, with a 0.4Ω (typ) on-resistance. This helps pre-
vent DL from being pulled up due to capacitive cou-
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