MAX1519 Datasheet, PDF (24/43 Pages) Maxim Integrated Products – Dual-Phase, Quick-PWM Controllers for Programmable CPU Core Power Supplies

Dual-Phase, Quick-PWM Controllers for
Programmable CPU Core Power Supplies
Table 5. Suspend Mode DAC Codes
LOWER SUSPEND CODES
UPPER SUSPEND CODES
SUS*
S1
OUTPUT
S0
VOLTAGE
(V)
OUTPUT
SUS*
S1
S0
VOLTAGE
(V)
High
GND
GND
0.675
REF
GND
GND
1.075
High
GND
REF
0.700
REF
GND
REF
1.100
High
GND
OPEN
0.725
REF
GND
OPEN
1.125
High
GND
V_CC
0.750
REF
GND
V_CC
1.150
High
REF
GND
0.775
REF
REF
GND
1.175
High
REF
REF
0.800
REF
REF
REF
1.200
High
REF
OPEN
0.825
REF
REF
OPEN
1.225
High
REF
V_CC
0.850
REF
REF
V_CC
1.250
High
OPEN
GND
0.875
REF
OPEN
GND
1.275
High
OPEN
REF
0.900
REF
OPEN
REF
1.300
High
OPEN
OPEN
0.925
REF
OPEN
OPEN
1.325
High
OPEN
V_CC
0.950
REF
OPEN
V_CC
1.350
High
V_CC
GND
0.975
REF
V_CC
GND
1.375
High
V_CC
REF
1.000
REF
V_CC
REF
1.400
High
V_CC
OPEN
1.025
REF
V_CC
OPEN
1.425
High
V_CC
V_CC
1.050
REF
V_CC
V_CC
1.450
*Connect the three-level SUS input to a 2.7V or greater supply (3.3V or V_CC) for an input logic level high.
troller ramps down to the 0V DAC code setting, it forces
the DL_ low-side gate-driver high, and pulls the DH_
high-side gate-driver low. Toggle SHDN or cycle the
V_CC power supply below 1V to clear the fault latch and
reactivate the controller after the junction temperature
cools by 15°C.
Thermal shutdown can be disabled through the “no-fault”
test mode (see the No-Fault Test Mode section).
No-Fault Test Mode
The latched-fault protection features and overlap mode
can complicate the process of debugging prototype
breadboards since there are (at most) a few milliseconds
in which to determine what went wrong. Therefore, a “no-
fault” test mode is provided to disable the fault protection
(overvoltage protection, undervoltage protection, and
thermal shutdown) and overlap mode. Additionally, the
test mode clears the fault latch if it has been set. The no-
fault test mode is entered by forcing 12V to 15V
on SHDN.
Multiphase Quick-PWM
5V Bias Supply (V_CC and V_DD)
The Quick-PWM controller requires an external 5V bias
supply in addition to the battery. Typically, this 5V bias
supply is the notebook’s 95%-efficient 5V system sup-
ply. Keeping the bias supply external to the IC
improves efficiency and eliminates the cost associated
with the 5V linear regulator that would otherwise be
needed to supply the PWM circuit and gate drivers. If
stand-alone capability is needed, the 5V bias supply
can be generated with an external linear regulator.
The 5V bias supply must provide V_CC (PWM controller)
and V_DD (gate-drive power), so the maximum current
drawn is:
I_BIAS = I_CC + f_SW(Q_G(LOW) + Q_G(HIGH))
where I_CC is provided in the Electrical Characteristics,
f_SW is the switching frequency, and Q_G(LOW) and Q_G(HIGH)
are the MOSFET data sheet’s total gate-charge specifi-
cation limits at V_GS = 5V. V+ and V_DD can be tied
together if the input power source is a fixed 4.5V to 5.5V
supply. If the 5V bias supply is powered up prior to the
battery supply, the enable signal (SHDN going from low
to high) must be delayed until the battery voltage is pre-
sent to ensure startup.
Free-Running, Constant On-Time PWM
Controller with Input Feed Forward
The Quick-PWM control architecture is a pseudo-fixed-
frequency, constant-on-time, current-mode regulator
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