MAX14920 Datasheet, PDF (5/29 Pages) Maxim Integrated Products – High-Accuracy 12-/16-Cell Measurement AFEs

MAX14920 / MAX14921
High-Accuracy 12-/16-Cell Measurement AFEs
DC ELECTRICAL CHARACTERISTICS (continued)
(V_P = +65V, DGND = AGND, V_L = V_EN = +3.3V, V_A = +5V, C_SAMPLE = 1FF, T_A = -40°C to +85°C, unless otherwise noted. Typical
values are at T_A = +25°C.) (Note 2)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX UNITS
Level-Shifting Delay Time
t_{LS_DELAY}
Delay from SMPLB set to 1 or SAMPL
falling edge to shifting of all cell voltages
to ground and available for reading
25
50
Fs
AOUT Voltage-Droop Time
T_ Settling Time
T_ Turn-On Delay Time
V_P Settling Time
Self-Calibration Time
t_DROOP Droop to -1mV (Figure 2)
1
ms
Measured between T_ input selection
t_TS
and AOUT settling to +1mV accuracy,
C_LOAD = 100pF, SC2 = 1
5
Fs
t_TD
0.2
Fs
Measured between V_P/12 (MAX14920),
t_VPS
V_P/16 (MAX14921) input selection and
AOUT, settling to 2.5%,
C_LOAD = 100pF, SC3 = 1
25
60
Fs
8
ms
THERMAL DETECTION
Thermal Shutdown
+140
°C
Thermal-Shutdown Hysteresis
15
°C
SPI TIMINGS (Figure 3)
SDI to SCLK Setup
SDI to SCLK Hold
SCLK to SDO Valid
CS Fall to SDO Enable
CS Rise to SDO Disable
CS Pulse Width
CS Fall to SCLK Rise Setup
CS Rise to SCLK Rise Hold
SCLK High Pulse Width
SCLK Low Pulse Width
SCLK Period
t_DS
t_DH
t_DO
t_DV
t_TR
t_CSW
t_CSS
t_CSH
t_CH
t_CL
t_CP
50
ns
12
ns
100
ns
100
ns
80
ns
50
ns
100
ns
0
ns
65
ns
65
ns
208
ns
Note 2: All devices are 100% production tested at T_A = +25°C. Limits over the operating temperature range are guaranteed by design.
Note 3: Where n = 1–12 (MAX14920) and n = 1–16 (MAX14921).
Note 4: Output error V_{O_ERR} is the difference between the input cell difference voltage (V_D = V_CV(n) - V_{CV(n - 1)}) and the
output voltage V_AOUT. Where n = 1–12 (MAX14920) and n = 1–16 (MAX14921). Output error depends on buffer ampli-
fier errors and parasitic capacitance charge injection error. Since parasitic capacitance error is PCB dependent, output
error is guaranteed by design for a sampling capacitor of 1FF and parasitic capacitance less than 2.5pF on CTn (see the
Measurement Accuracy section for a detailed explanation).
Note 5: Buffer amplifier self-calibrates its offset at power-up and every time it is requested. Due to possible thermal drift after
power-up phase, it is suggested to run self-calibration on a regular basis to get best performance
(see the Buffer Amplifier Offset Calibration section for a detailed explanation).
Note 6: Amplifier error is the sum of all errors including amplifier offset and gain error.
Maxim Integrated
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