MAX14920 Datasheet, PDF (13/29 Pages) Maxim Integrated Products – High-Accuracy 12-/16-Cell Measurement AFEs

MAX14920 / MAX14921
High-Accuracy 12-/16-Cell Measurement AFEs
Pin Description (continued)
PIN
MAX14920
MAX14921
(64 TQFP-EP) (80 TQFP)
51
67
52
68
53
69
54
70
55
71
56
72
57
73
58
74
59
75
60
76
61
77
62
78
63
79
64
80
—
15
—
16
—
17
NAME
FUNCTION
CV3
BA3
CT3
CB3
CV2
BA2
CT2
CB2
CV1
BA1
CT1
CV0
EN
CS
CV16
BA16
CT16
Cell Voltage Input 3. Connect CV3 to cell anode/cathode. Connect CV3 to the
highest voltage of the battery cell stack if not used.
Cell-Balancing Gate Driver Output 3. Connect BA3 to the gate of the external
n-channel FET. Leave BA3 unconnected if not used.
Sampling Capacitor 3 High Terminal. CT3 internally connects to CV3 when
SAMPL is logic-high. Connect a 1FF capacitor between CT3 and CB3. Leave CT3
unconnected if not used.
Sampling Capacitor 3 Low Terminal. CB3 internally connects to CV2 when
SAMPL is logic-high. Connect a 1FF capacitor between CT3 and CB3. Leave CB3
unconnected if not used.
Cell Voltage Input 2. Connect CV2 to cell anode/cathode. Connect CV2 to the
highest voltage of the battery cell stack if not used.
Cell-Balancing Gate Driver Output 2. Connect BA2 to the gate of the external
n-channel FET. Leave BA2 unconnected if not used.
Sampling Capacitor 2 High Terminal. CT2 internally connects to CV2 when
SAMPL is logic-high. Connect a 1FF capacitor between CT2 and CB2. Leave CT2
unconnected if not used.
Sampling Capacitor 2 Low Terminal. CB2 internally connects to CV1 when
SAMPL is logic-high. Connect a 1FF capacitor between CT2 and CB2. Leave CB2
unconnected if not used.
Cell Voltage Input 1. Connect CV1 to cell anode/cathode.
Cell-Balancing Gate Driver Output 1. Connect BA1 to the gate of the external
n-channel FET. Leave BA1 unconnected if not used.
Sampling Capacitor Connection 1 High Terminal. CT1 internally connects to CV1
when SAMPL is logic-high. Connect a 1FF capacitor between CT1 and CV0.
Leave CT1 unconnected if not used.
Cell Voltage Input 0. Connect CV0 to AGND.
Enable Input. Drive EN low to put the device into shutdown mode and reset the SPI
registers. The +5V LDO remains active in the shutdown mode. Drive EN high for
normal operation.
SPI Chip-Select Input. Active low.
Cell Voltage Input 16. Connect CV16 to cell anode/cathode. Connect CV16 to the
highest voltage of the battery cell stack if not used.
Cell-Balancing Gate Driver Output 16. Connect BA16 to the gate of the external
n-channel FET. Leave BA16 unconnected if not used.
Sampling Capacitor Connection 16 High Terminal. CT16 internally connects to
CV16 when SAMPL is logic-high. Connect a1FF capacitor between CT16 and CB16.
Leave CT16 unconnected if not used.
Maxim Integrated
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