MAX14920 Datasheet, PDF (24/29 Pages) Maxim Integrated Products – High-Accuracy 12-/16-Cell Measurement AFEs

MAX14920 / MAX14921
High-Accuracy 12-/16-Cell Measurement AFEs
Applications Information
Sampling Speed and Capacitor-
Selection Considerations
Capacitor values of 1FF are recommended for achieving
low errors and at high sampling rates, with sample and
hold times in the order of 5ms. With 1FF capacitors and
good PCB layout, charge injection-error correction is
normally not required.
If higher/lower sampling speeds are required, the sam-
pling capacitors and/or the series resistors at the cell
connections can be reduced and/or increased.
The cell sampling capacitors connected to the CT_ and
CB_ terminals affect:
• Speed of operation
• Cell readout accuracy
The smaller the sampling capacitor values, the lower
their RC time constant and hence the faster their charg-
ing time. Therefore, for higher-speed operation, smaller
capacitor values can be selected.
One application case can be when the cell voltages are
known to only vary by small amounts from one sample
to the next. In this case, the sampling capacitors can
be made smaller, as the sampling phases only need
to charge the capacitors by the charge lost during the
previous level shift and hold phase, including the small
change in cell voltage. See the Measurement Accuracy
section for details on how to calculate the voltage drop
due to these two factors. For example, sampling capaci-
tors of approximately 100nF can be adequate, thereby
reducing the sampling phase by a factor of 10. If this
technique is used, the initial sampling times, after initial
power-up, either have to be made longer to allow the ini-
tially discharged sampling capacitors to charge up to the
cell voltages, or the initial samples are disregarded until
the monitored voltages stabilize to their final cell value.
The accuracy dependence on the capacitor values is
determined by the discharge during the hold phase and
by the errors introduced during level shifting (both were
previously described). By speeding up the readout of
the cell voltages during the hold phase, discharging is
reduced. Note that the last cell voltage being read out
is most affected by discharging, due to its longer hold
delay until being read out. Smaller capacitor values are
prone to higher charge injection errors caused by level
shifting. Both low-capacitance layout and level-shift com-
pensation reduce these errors.
Typical Application Circuit
Figure 11 shows a high-accuracy measurement applica-
tion based on an accurate 16-bit ADC, together with a
high-quality voltage reference. The internal linear regula-
tor is used for supplying V_A (+5V), and uses the SAMPL
input for controlling the cell voltage sample and hold
times. Thermistors are connected to the T1, T2, and T3
inputs to monitor three temperatures.
If less absolute measurement accuracy is acceptable,
an ADC with internal reference, such as the MAX11163,
can be used. In applications where accuracy is not a
critical factor, a microcontroller’s internal ADC may be
adequate.
Multipack Applications
In applications that require more than 12/16 cells to
achieve higher voltages, multiple cell packs can be
stacked. Each pack in the stack does not have to have
the same number of cells. A minimum of +6V or 3 cells
can be monitored by the devices.
In stacked packs, the sample signal can either be cen-
trally controlled by a common signal for simultaneous
sampling, or the sample/hold can be initiated through
SPI. Two cell packs stacked on one another can be
interconnected through an SPI or other communication
interface. The packs can either have internal controllers
or multiple packs can be controlled by one common con-
troller. Internal controllers perform autonomous calibra-
tion and measurements, and allow an external controller
to collect the data on demand. This scheme is shown in
Figure 12. To translate the interpack communication sig-
nals between the differing common-mode pack voltages,
use opto-isolators, digital isolators, or digital ground level
shifters (Figure 12).
Layout Considerations
Keep the PCB traces to the sampling capacitors as short
as possible and minimize parasitic capacitance between
the capacitor pins and the ground plane.
Maxim Integrated
  24