MAX14920 Datasheet, PDF (16/29 Pages) Maxim Integrated Products – High-Accuracy 12-/16-Cell Measurement AFEs

MAX14920 / MAX14921
High-Accuracy 12-/16-Cell Measurement AFEs
SAMPLE PHASE
tSAMPL
HOLD PHASE
HOLD LEVEL
DELAY SHIFT
SETTLING
tD_H tD_LS _SELECT tSET _{CONVERT SELECT}
CELL a
CELL a CELL b
= VOLTAGE READY
= SPI ACTIVITY
= ADC CONVERSION
tSET _{CONVERT SELECT}
CELL b CELL c
CONVERT SELECT ^tSET CONVERT
CELL m CELL n
CELL n
Figure 5. SPI Control Cells Voltage Readout
Measurement Accuracy
The accuracy of cell voltage monitoring (i.e., the differ-
ence of the AOUT voltage relative to the cell voltages) is
determined by three factors:
1) Held voltage droop due to leakage on the CT_ pins
2) Internal buffer amplifier’s voltage errors
3) Capacitive level-shifting circuit error
The CT_ leakage (1FA, max) is a current that mainly
comes from the CV_ pin and increases with temperature.
Neglecting the PCB leakage across the sampling capaci-
tance, the voltage drift error is given by:
where:
V_{ERR_LEAK}
=
I_{CT _LEAK}
C _SAMPLE
x
t _READOUT
C_SAMPLE is the sampling capacitance
I_{CT_LEAK} is the leakage current on the CT_ pin
t_READOUT is the delay between hold starts and read-
out of the cell voltage
For example, with 1FF sampling capacitors and an ADC
conversion rate > 20kHz, V_{ERR_LEAK} is less than 1mV.
Cells with a higher common-mode voltage have a higher
leakage. To reduce the voltage drift over time, start
sequential voltage readout from the highest cell in the
stack first.
The buffer amplifier errors are nondeterministic in nature,
and vary from chip to chip. They are also affected by
temperature. The buffer amplifier offset error can be cali-
brated out through an internal offset-calibration function.
This calibration is automatically performed at power-up.
The calibration can also be initiated under SPI control.
Due to temperature drifts over time, it is best done on
a regular basis. Once the buffer amplifier offset is cali-
brated out, the total error of the buffer is below 0.3mV.
After power-up, if the devices do not calibrate regularly,
a temperature offset drift of Q1.5FV/NC can occur.
The level shifting is subject to deterministic errors due to
charge injection by parasitic PCB-related capacitance on
the CT_ pins. The charge-injected sampling error can be
calculated as follows:
V_{ERR_CHARGE_INJECTION} =
C_PAR
C _SAMPLE
x
V_CTn

x_
1−
1
e ^{−t SAMPL /(2RSW}

x
C
SAMPLE⁾


where:
C_PAR is the parasitic capacitance of the CTn pin,
where n = 1–12 (MAX14920) and n = 1–16 (MAX14921)
C_SAMPLE is the sampling capacitor
R_SW is the sampling switch resistance
V_CTn is the voltage of the CTn pin with respect to
AGND, where n = 1–12 (MAX14920) and n = 1–16
(MAX14921)
t_SAMPL is the sampling time
Maxim Integrated
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