MAX14920 Datasheet, PDF (22/29 Pages) Maxim Integrated Products – High-Accuracy 12-/16-Cell Measurement AFEs

MAX14920 / MAX14921
High-Accuracy 12-/16-Cell Measurement AFEs
Linear Regulator
The internal linear regulator has LDOIN as its input volt-
age and regulates this down to +5V Q5% at the V_A output
with a load current of 10mA (max). The LDO is automati-
cally enabled when LDOIN is above +5.5V. The internal
LDO is short-circuit protected with a current limit higher
than 14mA (22mA, typ). An external +5V regulator can be
used instead of the internal one. When using an external
+5V regular, LDOIN must be connected to V_A.
Thermal Protection
The devices have thermal shutdown to protect them
against thermal overheating. In thermal shutdown, the
LDO, amplifier, and charge-balance circuitry stop opera-
tion. The SPI interface is functional in thermal shutdown.
Shutdown Mode
The devices can be placed into low standby-power
shutdown mode through the LOPW bit. The internal LDO
remains on and the amplifier disabled, bringing the VP
supply current down to 1FA (max).
Analog/Temperature Inputs
The T1, T2, and T3 inputs are single-ended, CV0-
referenced, general-purpose analog inputs that are mul-
tiplexed to AOUT or to AOUT through a buffer (Figure 8).
These inputs can be used for connection of temperature
sensors or for a current monitor.
The total mux and switch series resistance is less than
200I. In applications where the load current flowing to the
AOUT output is so high that significant errors are introduced
due to series resistance in the voltage source and/or the
signal path, use the buffer amplifier to improve accuracy.
Route the T_ inputs through the buffer to AOUT by setting
the SPI bits [ECS, SC0, SC1, SC2, SC3] = [0, b, a, 1, 1].
Route the T_ inputs directly to the AOUT output by setting
the bits [ECS, SC0, SC1, SC2, SC3 = [0, b, a, 0, 1]. Bits
a and b select one of the three T_ inputs or three-state
the AOUT output.
Three-Stating the AOUT Output
The AOUT output can be three-stated to share this pin
with other external signal sources, such as additional
temperature sensors. Use the ECS and SC_ bits to three-
state the AOUT output.
Charge Balancing
Low-voltage enhancement-mode n-channel FETs can be
connected for passive balancing of cells. Select low on-
resistance FETs with a V_T less than V_BAH. Connect the
FETs between each cell’s anode and cathode through a
current-limiting resistor in the drain (Figure 9).
The charge-balancing FETs can be enabled through
SPI control. An internal 600I (typ)/900I (max) pulldown
resistor assures that the FET is normally switched off.
When balancing is active, a leakage current of 5FA is
sunk from CV_. In addition, an internal balancing current
flowing from CVn to CVn - 1 of 10mA (max) is present,
where n = 1–12 (MAX14920) and n = 1–16 (MAX14921).
The power dissipation created by the internal current
during balancing should be considered for total package
power management.
Diagnostics
The devices’ integrated diagnostics allow detection of
shorts between wires, as well as open-wire conditions of
the CV_ pins.
T1
AOUT
T2
BUFFER
T3
SPI CONTROL
Figure 8. Analog/ Temperature Measurement
Maxim Integrated
CVn*
RBAL
CELLn*
BAn*
CVn* - 1
BAL
600I
MAX14920
MAX14921
*n = 1–12 (MAX14920) and n = 1–16 (MAX14921)
Figure 9. Charge Balancing
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