MAX14920 Datasheet, PDF (15/29 Pages) Maxim Integrated Products – High-Accuracy 12-/16-Cell Measurement AFEs

MAX14920 / MAX14921
High-Accuracy 12-/16-Cell Measurement AFEs
Detailed Description
The MAX14920/MAX14921 analog front-end devices are
used in multicell battery measurement systems to moni-
tor primary/secondary battery packs up to 16 cells/+65V
(max). The devices perform the signal conditioning
required for enabling accurate cell voltage measurement.
Both devices simultaneously sample all cell voltages,
allowing accurate state-of-charge and source-resistance
determination, even under transient load current condi-
tions. The cell voltage measurements are shifted down to
ground reference with unity gain, simplifying external ADC
data conversion. The devices enable passive cell balanc-
ing through drivers that control external discharge FETs.
A high-accuracy, low-offset amplifier buffers differen-
tial voltages up to +5V for monitoring of the common
rechargeable cell technologies such as lithium-ion (Li+).
The resulting cell measurement errors from the devices
are below Q0.5mV (max). The devices’ high accuracy
make them ideal for monitoring cell chemistries with very
flat discharge curves, such as a lithium-metal phosphate
cell. Diagnostics detect open-wire and short conditions,
and warn about overvoltage/undervoltage.
The SPI interface is used for control and monitoring
through a host controller. The SPI interface is daisy-
chainable. Both devices can operate with a minimum of
+6V total stack voltage (typically equating to 3 cells).
Voltage Sampling
The voltages of all cells are tracked by the sampling
capacitors connected between the CTn and CBn pins
(where n = 1–12 (MAX14920) and n = 1–16 (MAX14921)),
while the SMPLB bit is set to 0 and the SAMPL input is
driven high (Figure 4). When the SMPLB bit is set to 1,
and the SAMPL input transitions low, all cell voltages are
simultaneously sampled on their associated capacitors.
The voltages are held by the capacitors while the SMPLB
bit is 1, or the SAMPL pin is held low. When sample and
holding is controlled by the SAMPL input, set the SMPLB
bit to 0. When sample and hold is controlled by the
SMPLB bit, keep the SAMPL input high.
In sample phase selecting any cell voltage (ECS = 1),
AOUT equals V_P/12 (MAX14920) or V_P/16 (MAX14921).
Resistors can be placed in series with the CV_ inputs
to filter transients and/or for protection. Consider the
switches’ on-resistance of 150I (max) when calculating
the filter and settling times. In the holding phase, each
capacitor’s voltage can be independently routed to the
analog AOUT output under SPI control.
Voltage Readout
When the SMPLB bit is set high, or when the SAMPL input
is driven low, the sampling switches are opened after
0.5Fs (typ) and the cell voltages are held on the external
sampling capacitors. Within the time of t_{LS_DELAY} < 50Fs
(max), the capacitors’ voltages are all shifted to ground
reference. Then the undervoltage/overvoltage monitor-
ing of all cells is valid and the cell voltage is available
for sequential readout under SPI control. The SPI control
can select the readout of any cell voltages, in any order
(Figure 5).
With the ECS bit set to 1, a selected cell’s voltage appears
at the AOUT output according to the cell selection (as
defined by the SC_ cell select bits). A low-leakage, low-
noise, low-offset amplifier buffers the capacitor charge
and provides the high-accuracy AOUT analog output.
After a settling time of t_SET, from the rising edge of the
CS signal, the voltage is available at AOUT with speci-
fied accuracy. An ADC can then sample and convert the
AOUT voltage. The AOUT output voltage droops over
time due to capacitor discharge. The droop time for 1mV
of change is larger than t_DROOP (> C_SAMPLE/I_{CT_LEAK}).
CVn*
CVn* - 1
SAMPL
CSAMPLE
CTn*
CBn*
MAX14920
MAX14921
SMPLB
*n = 1–12 (MAX14920) and n = 1–16 (MAX14921)
Figure 4. Voltage Sampling
Maxim Integrated
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