MAX11634 Datasheet, PDF (5/24 Pages) Maxim Integrated Products – 12-Bit, 300ksps ADCs with Differential

12-Bit, 300ksps ADCs with Differential
Track/Hold, and Internal Reference
TIMING CHARACTERISTICS (Figure 1)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX UNITS
Externally clocked conversion
208
SCLK Clock Period
t_CP
ns
Data I/O
100
SCLK Pulse-Width High
t_CH
SCLK Pulse-Width Low
t_CL
40
ns
40
ns
SCLK Fall to DOUT Transition
CS Rise to DOUT Disable
CS Fall to DOUT Enable
DIN to SCLK Rise Setup
t_DOT
t_DOD
t_DOE
t_DS
C_LOAD = 30pF
C_LOAD = 30pF
C_LOAD = 30pF
40
ns
40
ns
40
ns
40
ns
SCLK Rise to DIN Hold
CS Low to SCLK Setup
CS High to SCLK Setup
CS High After SCLK Hold
CS Low After SCLK Hold
t_DH
t_CSS0
t_CSS1
t_CSH1
t_CSH0
0
ns
40
ns
40
ns
0
ns
0
4
µs
CNVST Pulse-Width Low
t_CSPW
CKSEL = 00
CKSEL = 01
40
ns
1.4
µs
CS or CNVST Rise to EOC
Low (Note 11)
Voltage conversion
Reference power-up
7
µs
65
Note 11: This time is defined as the number of clock cycles needed for conversion multiplied by the clock period. If the internal
reference needs to be powered up, the total time is additive. The internal reference is always used for temperature
measurements.
Typical Operating Characteristics
(V_DD = 3V, V_REF = 2.5V, f_SCLK = 4.8MHz, C_LOAD = 30pF, T_A = +25°C for MAX11635/MAX11637, unless otherwise noted. V_DD = 5V,
V_REF = 4.096V, f_SCLK = 4.8MHz, C_LOAD = 30pF, T_A = +25°C for MAX11634/MAX11636, unless otherwise noted.)
1.0
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1.0
0
INTEGRAL NONLINEARITY
vs. OUTPUT CODE
MAX11634/MAX11636
f_SAMPLE = 300ksps
1024
2048
3072
4096
OUTPUT CODE (DECIMAL)
1.0
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1.0
0
INTEGRAL NONLINEARITY
vs. OUTPUT CODE
MAX11635/MAX11637
f_SAMPLE = 300ksps
1024
2048
3072
4096
OUTPUT CODE (DECIMAL)
1.0
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1.0
0
DIFFERENTIAL NONLINEARITY
vs. OUTPUT CODE
MAX11634/MAX11636
f_SAMPLE = 300ksps
1024
2048
3072
4096
OUTPUT CODE (DECIMAL)
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