MAX11634 Datasheet, PDF(15/24 Page) Maxim Integrated Products – 12-Bit, 300ksps ADCs with Differential

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MAX11634 Datasheet, PDF (15/24 Pages) Maxim Integrated Products – 12-Bit, 300ksps ADCs with Differential

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12-Bit, 300ksps ADCs with Differential

Track/Hold, and Internal Reference

Table 2. Conversion Register*

BIT

NAME BIT

FUNCTION

â 7 (MSB) Set to 1 to select conversion register

6 Donât care

CHSEL2 5 Analog input channel select

CHSEL1 4 Analog input channel select

CHSEL0 3 Analog input channel select

SCAN1 2 Scan mode select

SCAN0 1 Scan mode select

X 0 (LSB) Donât care

*See below for bit details.

CHSEL2

CHSEL1

CHSEL0

SELECTED

CHANNEL (N)

AIN0

AIN1

AIN2

AIN3

AIN4

AIN5

AIN6

AIN7

SCAN1 SCAN0

SCAN MODE (CHANNEL N IS

SELECTED BY BITS CHSEL[2:0])

0 Scans channels 0 through N

Scans channels N through the highest

numbered channel

Scans channel N repeatedly. The averaging

1 No scan. Converts channel N once only.

Setup Register

Write a byte to the setup register to configure the clock,

reference, and power-down modes. Table 3 details the

bits in the setup register. Bits 5 and 4 (CKSEL1 and

CKSEL0) control the clock mode, acquisition and sam-

pling, and the conversion start. Bits 3 and 2 (REFSEL1

and REFSEL0) control internal or external reference use.

Bits 1 and 0 (DIFFSEL1 and DIFFSEL0) address the

unipolar mode and bipolar mode registers and configure

the analog input channels for differential operation.

Unipolar/Bipolar Mode Registers

The final 2 bits (LSBs) of the setup register control the

unipolar/bipolar mode address registers. Set bits 1 and

0 (DIFFSEL1 and DIFFSEL0) to 10 to write to the unipo-

lar mode register. Set bits 1 and 0 to 11 to write to the

bipolar mode register. In both cases, the setup byte

must be followed immediately by 1 byte of data written

to the unipolar register or bipolar register. Hold CS low

and run 16 SCLK cycles before pulling CS high. If the

last 2 bits of the setup register are 00 or 01, neither the

unipolar mode register nor the bipolar mode register is

written. Any subsequent byte is recognized as a new

input data byte. See Tables 4 and 5 to program the

unipolar and bipolar mode registers.

If a channel is configured as both unipolar and bipolar,

the unipolar setting takes precedence. In unipolar

mode, AIN+ can exceed AIN- by up to VREF. The out-

put format in unipolar mode is binary. In bipolar mode,

either input can exceed the other by up to VREF/2. The

output format in bipolar mode is two's complement.

Averaging Register

Write to the averaging register to configure the ADC to

average up to 32 samples for each requested result,

and to independently control the number of results

requested for single-channel scans.

Table 2 details the four scan modes available in the con-

version register. All four scan modes allow averaging as

long as the AVGON bit, bit 4 in the averaging register, is

set to 1. Select scan mode 10 to scan the same channel

multiple times. Clock mode 11 disables averaging.

Reset Register

Write to the reset register (as shown in Table 7) to clear

the FIFO or to reset all registers to their default states.

Set the RESET bit to 1 to reset the FIFO. Set the RESET

bit to zero to return the MAX11634âMAX11637 to the

default power-up state.

Power-Up Default State

The MAX11634âMAX11637 power up with all blocks in

shutdown, including the reference. All registers power up

in state 00000000, except for the setup register, which

powers up in clock mode 10 (CKSEL1 = 1).

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