MAX11634 Datasheet, PDF (21/24 Pages) Maxim Integrated Products – 12-Bit, 300ksps ADCs with Differential

12-Bit, 300ksps ADCs with Differential
Track/Hold, and Internal Reference
DIN
CS
SCLK
(CONVERSION BYTE)
(ACQUISITION1)
(CONVERSION1)
(ACQUISITION2)
DOUT
MSB1
LSB1
MSB2
EOC
EXTERNALLY TIMED ACQUISITION, SAMPLING AND CONVERSION WITHOUT CNVST.
Figure 7. Clock Mode 11
Partial Reads and Partial Writes
If the first byte of an entry in the FIFO is partially read
(CS is pulled high after fewer than eight SCLK cycles),
the second byte of data that is read out contains the
next 8 bits (not b[7:0]). The remaining bits are lost for
that entry. If the first byte of an entry in the FIFO is read
out fully, but the second byte is read out partially, the
rest of the entry is lost. The remaining data in the FIFO
is uncorrupted and can be read out normally after tak-
ing CS low again, as long as the four leading bits (nor-
mally zeros) are ignored. Internal registers that are
written partially through the SPI contain new values,
starting at the MSB up to the point that the partial write
is stopped. The part of the register that is not written
contains previously written values. If CS is pulled low
before EOC goes low, a conversion cannot be complet-
ed and the FIFO is corrupted.
Transfer Function
Figure 8 shows the unipolar transfer function for single-
ended or differential inputs. Figure 9 shows the bipolar
transfer function for differential inputs. Code transitions
occur halfway between successive-integer LSB values.
Output coding is binary, with 1 LSB = V_REF/4096 for
unipolar and bipolar operation, and 1 LSB = 0.125°C
for temperature measurements.
Layout, Grounding, and Bypassing
For best performance, use PC boards. Do not use wire-
wrap boards. Board layout should ensure that digital
and analog signal lines are separated from each other.
Do not run analog and digital (especially clock) signals
parallel to one another or run digital lines underneath the
MAX11634–MAX11637 package. High-frequency noise
in the V_DD power supply can affect performance.
Bypass the V_DD supply with a 0.1µF capacitor to GND,
close to the V_DD pin. Minimize capacitor lead lengths for
best supply-noise rejection. If the power supply is very
noisy, connect a 10Ω resistor in series with the supply to
improve power-supply filtering.
Definitions
Integral Nonlinearity
Integral nonlinearity (INL) is the deviation of the values
on an actual transfer function from a straight line. This
straight line can be either a best-straight-line fit or a line
drawn between the end points of the transfer function,
once offset and gain errors have been nullified. INL for
the MAX11634–MAX11637 is measured using the end-
point method.
Differential Nonlinearity
Differential nonlinearity (DNL) is the difference between
an actual step width and the ideal value of 1 LSB. A
DNL error specification of less than 1 LSB guarantees
no missing codes and a monotonic transfer function.
Aperture Jitter
Aperture jitter (t_AJ) is the sample-to-sample variation in
the time between the samples.
Aperture Delay
Aperture delay (t_AD) is the time between the rising
edge of the sampling clock and the instant when an
actual sample is taken.
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