MAX11634 Datasheet, PDF (13/24 Pages) Maxim Integrated Products – 12-Bit, 300ksps ADCs with Differential

12-Bit, 300ksps ADCs with Differential
Track/Hold, and Internal Reference
AIN0–AIN7
(SINGLE-ENDED);
AIN0, AIN2,
AIN4, AIN6
(DIFFERENTIAL)
HOLD
GND
(SINGLE-ENDED);
AIN1, AIN3,
AIN5, AIN7
(DIFFERENTIAL)
REF
GND
DAC
CIN+
CIN-
HOLD
V_DD/2
COMPARATOR
+
-
HOLD
Figure 3. Equivalent Input Circuit
Unipolar/Bipolar
Address the unipolar and bipolar registers through the
setup register (bits 1 and 0). Program a pair of analog
channels for differential operation by writing a 1 to the
appropriate bit of the bipolar or unipolar register.
Unipolar mode sets the differential input range from 0
to V_REF. A negative differential analog input in unipolar
mode causes the digital output code to be zero.
Selecting bipolar mode sets the differential input range
to ±V_REF/2. The digital output code is binary in unipolar
mode and two’s complement in bipolar mode (Figures
8 and 9).
In single-ended mode, the MAX11634–MAX11637
always operate in unipolar mode. The analog inputs are
internally referenced to GND with a full-scale input
range from 0 to V_REF.
True Differential Analog Input T/H
The equivalent circuit of Figure 3 shows the
MAX11634–MAX11637s’ input architecture. In track
mode, a positive input capacitor is connected to
AIN0–AIN7 in single-ended mode (and AIN0, AIN2,
AIN4, AIN5, AIN6 in differential mode). A negative input
capacitor is connected to GND in single-ended mode
(or AIN1, AIN3, AIN5, AIN6, AIN7 in differential mode).
For external T/H timing, use clock mode 01. After the
T/H enters hold mode, the difference between the sam-
pled positive and negative input voltages is converted.
The time required for the T/H to acquire an input signal
is determined by how quickly its input capacitance is
charged. If the input signal’s source impedance is high,
the required acquisition time lengthens. The acquisition
time, t_ACQ, is the maximum time needed for a signal to
be acquired, plus the power-up time. It is calculated by
the following equation:
t_ACQ = 9 x (R_S + R_IN) x 24pF + t_PWR
where R_IN = 1.5kΩ, R_S is the source impedance of the
input signal, and t_PWR = 1µs, the power-up time of the
device. The varying power-up times are detailed in the
explanation of the clock mode conversions.
When the conversion is internally timed, t_ACQ is never
less than 1.4µs, and any source impedance below
300Ω does not significantly affect the ADC’s AC perfor-
mance. A high-impedance source can be accommo-
dated either by lengthening t_ACQ or by placing a 1µF
capacitor between the positive and negative analog
inputs.
Internal FIFO
The MAX11634–MAX11637 contain a FIFO buffer that
can hold up to 16 ADC results. This allows the ADC to
handle multiple internally clocked conversions without
tying up the serial bus.
If the FIFO is filled and further conversions are requested
without reading from the FIFO, the oldest ADC results
are overwritten by the new ADC results. Each result
contains 2 bytes, with the MSB preceded by four lead-
ing zeros. After each falling edge of CS, the oldest
available byte of data is available at DOUT, MSB first.
When the FIFO is empty, DOUT is zero.
Internal Clock
The MAX11634–MAX11637 operate from an internal
oscillator, which is accurate within 10% of the 4.4MHz
nominal clock rate. The internal oscillator is active in
clock modes 00, 01, and 10. Read out the data at clock
speeds up to 10MHz. See Figures 4–7 for details on
timing specifications and starting a conversion.
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