MAX11634 Datasheet, PDF (10/24 Pages) Maxim Integrated Products – 12-Bit, 300ksps ADCs with Differential

12-Bit, 300ksps ADCs with Differential
Track/Hold, and Internal Reference
Pin Configuration
TOP VIEW
+
AIN0 ₁
AIN1 2
AIN2 3
AIN3 4
AIN4 (N.C.) 5
MAX11634–
MAX11637
AIN5 (N.C.) 6
REF-/AIN6 (REF-) 7
CNVST/AIN7 (CNVST) 8
QSOP
16 EOC
15 DOUT
14 DIN
13 SCLK
12 CS
11 V_DD
10 GND
9 REF+
( ) PINOUT FOR THE MAX11634/MAX11635.
Pin Description
PIN
MAX11634 MAX11636
MAX11635 MAX11637
1–4
—
5, 6
—
7
—
8
—
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
—
1–6
—
7
—
8
NAME
FUNCTION
AIN0–AIN3
N.C.
REF-
Analog Inputs
No Connection. Not internally connected.
External Differential Reference Negative Input
CNVST
Active-Low Conversion Start Input. See Table 3 for details on programming the
setup register.
REF+
GND
V_DD
CS
Positive Reference Input. Bypass to GND with a 0.1µF capacitor.
Ground
Power Input. Bypass to GND with a 0.1µF capacitor.
Active-Low Chip-Select Input. When CS is high, DOUT is high impedance.
SCLK
Serial-Clock Input. Clocks data in and out of the serial interface (duty cycle must
be 40% to 60%). See Table 3 for details on programming the clock mode.
DIN
Serial-Data Input. DIN data is latched into the serial interface on the rising edge of
SCLK.
DOUT
EOC
AIN0–AIN5
Serial-Data Output. Data is clocked out on the falling edge of SCLK. High
impedance when CS is connected to V_DD.
Active-Low End-of-Conversion Output. Data is valid after EOC pulls low.
Analog Inputs
External Differential Reference Negative Input/Analog Input 6. See Table 3 for
REF-/AIN6 _{details on programming the setup register.}
CNVST/AIN7
Active-Low Conversion Start Input/Analog Input 7. See Table 3 for details on
programming the setup register.
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