MAX11158 Datasheet, PDF (5/26 Pages) Maxim Integrated Products – 500ksps Throughput Rates Without Pipeline

MAX11158
18-Bit, 500ksps, ±5V SAR ADC with
Internal Reference in µMAX
Electrical Characteristics (continued)
(V_DD = 4.75V to 5.25V, V_OVDD = 2.3V to 5.25V, f_SAMPLE = 500ksps, T_A = T_MIN to T_MAX, unless otherwise noted. Typical values are
at T_A = +25°C.) (Note 2)
PARAMETER
CNVST Low to SDO D15 MSB Valid
(CS Mode)
CNVST High or SDI High or Last
SCLK Falling Edge to SDO High
Impedance
SYMBOL
t_EN
t_DIS
CONDITIONS
V_OVDD > 2.7V
V_OVDD < 2.7V
CS mode
SDI Valid Setup Time from CNVST
Rising Edge
t_SSDICNV 4-wire CS mode
SDI Valid Hold Time from CNVST
Rising Edge
t_HSDICNV 4-wire CS mode
SCLK Valid Setup Time from CNVST
Rising Edge
t_SSCKCNV
Daisy-chain mode
SCLK Valid Hold Time from CNVST
Rising Edge
SDI Valid Setup Time from SCLK
Falling Edge
SDI Valid Hold Time from SCLK
Falling Edge
t_HSCKCNV Daisy-chain mode
t_SSDISCK
Daisy-chain mode, V_OVDD > 4.5V
Daisy-chain mode, V_OVDD > 2.7V
Daisy-chain mode, V_OVDD > 2.3V
t_HSDISCK Daisy-chain mode
Daisy-chain mode with busy indicator,
V_OVDD > 4.5V
SDI High to SDO High
t_DSDOSDI
Daisy-chain mode with busy indicator,
V_OVDD > 2.7V
Daisy-chain mode with busy indicator,
V_OVDD > 2.3V
MIN TYP MAX UNITS
14
ns
18
20
ns
5
ns
0
ns
3
ns
3
ns
3
5
ns
6
0
ns
10
15
ns
20
Note 2: Maximum and minimum limits are fully production tested over specified supply voltage range and at a temperature of
+25°C. Limits over the operating temperature range are guaranteed by design and device characterization.
Note 3: See the Analog Inputs and Overvoltage Input Clamps sections.
Note 4: Static Performance limits are guaranteed by design and device characterization.
Note 5: Defined as the change in positive full-scale code transition caused by a ±5% variation in the V_DD supply voltage.
Note 6: 10kHz sine wave input, -0.1dB below full scale.
Note 7: f_IN1 ~ 9.4kHz, f_IN2 ~ 10.7kHz, Each tone at 6.1dB below full scale.
Note 8: C_LOAD = 65pF on SDO.
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