MAX11158 Datasheet, PDF (15/26 Pages) Maxim Integrated Products – 500ksps Throughput Rates Without Pipeline

MAX11158
18-Bit, 500ksps, ±5V SAR ADC with
Internal Reference in µMAX
Transfer Function
The ideal transfer characteristic for the MAX11158 is
shown in Figure 3. The precise location of various points
on the transfer function are given in Table 2.
Digital Interface
The MAX11158 includes three digital inputs (CNVST, SCLK,
and SDI) and a single digital output (SDO). The ADC can
be configured for one of six interface modes, allowing the
device to support a wide variety of application needs.
The 3-wire and 4-wire CS interface modes are compat-
ible with SPI, QSPI, digital hosts, and DSPs. The 3-wire
interface uses CNVST, SCLK, and SDO for minimal wiring
complexity and is ideally suited for isolated applications.
The 4-wire interface allows CNVST to be independent of
output data readback (SDI) affording the highest level of
individual device control. This configuration is useful for low
jitter or multichannel, simultaneously sampled applications.
The 3-wire daisy-chain mode is the easiest way to config-
ure a multichannel, simultaneous-sampling system. This
system is built by cascading multiple ADCs into a shift
register structure. The CNVST and SCLK inputs are com-
mon to all ADCs, while the SDO output of one device feeds
the SDI input of the next device in the chain. The 3-wire
interface is simply the CNVST, SCLK, and SDO of the last
ADC in the chain.
The selection of CS or daisy-chain modes is controlled by
the SDI logic level during the rising edge of CNVST. The
CS mode is selected if SDI is high and the daisy-chain
mode is selected if SDI is low. If SDI and CNVST are con-
nected together, the daisy-chain mode is selected.
In each of the three modes described above (3-wire
CS mode, 4-wire CS mode, and daisy-chain mode), the
user must externally time out the maximum ADC conver-
sion time before commencing readback. Alternatively, the
MAX11158 offers a busy indicator feature on SDO in each
mode to eliminate external timer circuits.
When busy indication is enabled, SDO provides a busy
indicator bit to signal the end of conversion. One additional
SCLK is required to flush the SDO busy indication bit prior
to reading back the data. Busy indicator is enabled in CS
Table 2. Transfer Function Example
mode if CNVST or SDI is low when the ADC conversion
completes. In daisy-chain mode, the busy indicator is
selected based on the state of SCLK at the rising edge
of CNVST. If SCLK is high, the busy indicator is enabled;
otherwise, the busy indicator is not enabled.
The following sections provide specifics for each of the
six serial interface modes. Due to the possibility of perfor-
mance degradation, digital activity should only occur after
conversion is completed or limited to the first half of the
conversion phase. Having SCLK or SDI transitions near
the sampling instant can also corrupt the input sample
accuracy. Therefore, keep the digital inputs quiet for
approximately 25ns before and 10ns after the rising edge
of CNVST. These times are denoted as t_SSCKCNV and
t_HSCKCNV in all subsequent timing diagrams.
In all interface modes, the data on SDO is valid on both
SCLK edges. However, input setup time into the receiving
host will be maximized when data is clocked into that host
on the falling SCLK edge. Doing so will allow for higher
data transfer rates between the MAX11158 and the receiv-
ing host and consequently higher converter throughput.
3FFFF
3FFFE
20001
20000
+FS = ^{+5 × VREF}
4.096
-FS = ^{-5 × VREF}
4.096
+FS - (-FS)
LSB =
262144
TRANSITION
1FFFF
1FFFE
000001
000000
-FS
0
-FS + 0.5 × LSB
INPUT VOLTAGE (LSB)
Figure 3. Bipolar Transfer Function
+FS - 1 LSB
+FS
+FS - 1.5 × LSB
CODE TRANSITION
+FS - 1.5 LSB
Midscale + 0.5 LSB
Midscale
Midscale - 0.5 LSB
-FS + 0.5 LSB
BIPOLAR INPUT (V)
+4.999943
+0.000019
0
-0.000019
-4.999981
DIGITAL OUTPUT CODE (HEX)
3FFFE - 3FFFF
20000 - 20001
20000
1FFFF - 20000
00000 - 00001
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