MAX11158 Datasheet, PDF (11/26 Pages) Maxim Integrated Products – 500ksps Throughput Rates Without Pipeline

MAX11158
Pin Configuration
18-Bit, 500ksps, ±5V SAR ADC with
Internal Reference in µMAX
TOP VIEW
REF
VDD
AIN+
AIN-
GND
1⁺
10
2
9
3 ^{MAX11158 8}
4
7
5
6
µMAX
OVDD
SDI
SCLK
SDO
CNVST
Pin Description
PIN NAME
FUNCTION
1
REF
Internal Reference Bypass. Bypass to GND in close proximity with a X5R or X7R 10μF 16V capacitor. See
the Layout, Grounding, and Bypassing section.
2
V_DD
Analog Power Supply. Bypass V_DD to GND with a 0.1µF capacitor as close as possible to each device and
one 10µF capacitor per board.
3
AIN+ Positive Analog Input
4
AIN- Negative Analog Input. Connect AIN- to the analog ground plane or to a remote sense ground.
5
GND Power-Supply Ground
Conversion Start Input. The rising edge of CNVST initiates the conversions and selects the interface mode:
6
CNVST daisy-chain or CS. In CS mode, either SDI or CNVST can enable the serial output signals when low. If SDI or
CNVST is low when the conversion is completed, the busy indicator feature is enabled..
7
SDO Serial Data Output. SDO transitions on the falling edge of SCLK.
8
SCLK Serial Clock Input. Clocks data out of the serial interface when the device is selected.
Serial Data Input and Mode Select Input. Daisy-chain mode is selected if SDI is low during the CNVST rising
edge. In this mode, SDI is used as a data input to daisy-chain the conversion results of two or more ADCs
9
SDI onto a single SDO line. CS mode is selected if SDI is high during the CNVST rising edge. In this mode, either
SDI or CNVST can enable the serial output signals when low. If SDI or CNVST is low when the conversion is
completed, the busy indicator feature is enabled.
10
OVDD
Digital Power Supply. OVDD can range from 2.3V to V_DD. Bypass OVDD to GND with a 0.1µF capacitor for
each device and one 10µF per board.
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