MAX11158 Datasheet, PDF (21/26 Pages) Maxim Integrated Products – 500ksps Throughput Rates Without Pipeline

MAX11158
18-Bit, 500ksps, ±5V SAR ADC with
Internal Reference in µMAX
CONVERT
CNVST
SDI
MAX11158 SDO
Device A
SCLK
SDOA
CNVST
SDI
MAX11158 SDO
Device B
SCLK
SDOB
DIGITAL HOST
DATA IN
Figure 13. Daisy-Chain Mode, No-Busy Indicator Connection Diagram
tCYC
CNVST
ACQUISITION
tSSCKCNV
SCLK
SDOA = SDIB
SDOB
tCONV
CONVERSION
tHSCKCNV
SELECT NO
BUSY
OUTPUT
SELECT CHAIN
MODE
tACQ
ACQUISITION
tSCLK
tSCLKL
1
2
3
16
17
18
19
20
tSSDISCK
tSCLKH
tHSDISCK
DA17
DA16
DA15
DA1
DA0
tDSDO
DB17
DB16
DB15
DB1
DB0
DA17
DA16
CLK
34
35
36
DA1
DA0
tCNVPW
Figure 14. Daisy-Chain Mode, No-Busy Indicator Serial Interface Timing
Daisy-Chain Mode, No-Busy Indicator
The daisy-chain mode with no-busy indicator is ideally suit-
ed for multichannel isolated applications that require mini-
mal wiring complexity. Simultaneous sampling of multiple
ADC channels is realized on a 3-wire serial interface where
data readback is analogous to clocking a shift register. In
Figure 13, two ADCs are connected to an SPI-compatible
digital host with corresponding timing given in Figure 14.
The daisy-chain mode is engaged when the MAX11158
detects the low state on SDI at the rising edge of CNVST.
In this mode, CNVST is brought low and then high to trigger
the completion of the acquisition phase and the start of a
conversion. A low SCLK state on the rising edge of CNVST
signals to the internal controller that the no-busy indicator
will be output. When in chain mode, the SDO output is
driven active at all times.
When SDI and CNVST are both low, SDO is driven low,
thus engaging the daisy-chain mode of operations on the
downstream MAX11158 parts. For example, in Figure 13
part A has its SDI tied low so the chain mode of operation
will be selected on every conversion. When CNVST goes
low to trigger another conversion, part A’s SDO and con-
sequently part B’s SDI go low as well. On the next CNVST
rising edge both parts A and B will select the daisy-chain
mode interface.
When a conversion is complete, the MSB is presented onto
SDO, and the MAX11158 returns to the acquisition phase.
The remaining data bits, stored within the internal shift
register, are clocked out on each subsequent SCLK falling
edge. The SDI input of each ADC in the chain is used to
transfer conversion data from the previous ADC into the
internal shift register of the next ADC, thus allowing for data
to be clocked through the multichip chain on each SCLK
falling edge. Each ADC in the chain outputs its MSB data
first requiring 18 × N clocks to read back N ADCs.
In daisy-chain mode, the maximum conversion rate is
reduced due to the increased readback time. For instance,
with a 6ns digital host setup time and 3V interface, up to
four MAX11158 devices running at a conversion rate of
310ksps can be daisy-chained on a 3-wire port.
www.maximintegrated.com
Maxim Integrated │  21