MAX11158 Datasheet, PDF (20/26 Pages) Maxim Integrated Products – 500ksps Throughput Rates Without Pipeline

MAX11158
18-Bit, 500ksps, ±5V SAR ADC with
Internal Reference in µMAX
CNVST
SDI
MAX11158 SDO
SCLK
OVDD
10kΩ
CS1
CONVERT
DIGITAL HOST
DATA IN
IRQ
CLK
Figure 11. CS Mode 4-Wire with Busy Indicator Connection Diagram
CNVST
ACQUISITION
tSSDICNV
SDI
SCLK
SDO
tCONV
CONVERSION
tHSDICNV
tSSCKCNV
tHSCKCNV
tCYC
tCNVPW
tACQ
ACQUISITION
1
2
tDSDO
tSCLK
tSCLKL
3
17
18
19
tSCLKH
tDIS
BUSY BIT
D17
D16
D1
D0
Figure 12. CS Mode 4-Wire with Busy Indicator Serial Interface Timing
CS Mode 4-Wire, With Busy Indicator
The 4-wire CS mode with busy indicator is shown in Figure
11 where a single ADC is connected to an SPI-compatible
digital host with interrupt input. The corresponding timing
is given in Figure 12. This mode is ideally suited for single
ADC applications where the CNVST pin may be used for
low-jitter sampling while the SDI pin is used for data read-
back.
With SDI high, a rising edge on CNVST completes the
acquisition, initiates the conversion and forces SDO to high
impedance. This mode requires CNVST to be held high
during the conversion and data readback phases. Note
that if CNVST and SDI are low, SDO is driven low. During
the conversion, the SDI pin can be used as a select line
for other devices on the board, but must be returned low
before the minimum conversion time and held low until the
busy signal is generated.
When the conversion is complete SDO transitions from
high impedance to a low logic level signaling to the digital
host through the interrupt input that data readback can
commence. The MAX11158 then enters the acquisition
phase. The data bits are clocked out, MSB first, by subse-
quent SCLK falling edges. SDO returns to high impedance
after the 19th SCLK falling edge or when CNVST goes
high and is then pulled to OVDD through the external
pullup resistor.
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