MAX11158 Datasheet, PDF (23/26 Pages) Maxim Integrated Products – 500ksps Throughput Rates Without Pipeline

MAX11158
18-Bit, 500ksps, ±5V SAR ADC with
Internal Reference in µMAX
The conversion data bits are stored within the internal shift
register and clocked out on each subsequent SCLK falling
edge. The SDI input of each ADC in the chain is used to
transfer conversion data from the previous ADC into the
internal shift register of the next ADC, thus allowing for data
to be clocked through the multichip chain on each SCLK
falling edge. With busy indicator mode selected, the busy
bit from each part is not chained on the first falling SCLK
edge in the readout pattern. Consequently, the number of
falling SCLKs needed to read back all data from N ADCs is
18 × N + 1 falling edges.
In daisy-chain mode, the maximum conversion rate is
reduced due to the increased readback time. For instance,
with a 6ns digital host setup time and 3V interface, up to
four MAX11158 devices running at a conversion rate of
308ksps can be daisy-chained on a 3-wire port.
Layout, Grounding, and Bypassing
For best performance, use PCBs with ground planes.
Ensure that digital and analog signal lines are separated
from each other. Do not run analog and digital lines paral-
lel to one another (especially clock lines), and avoid run-
ning digital lines underneath the ADC package. A single
solid GND plane configuration with digital signals routed
from one direction and analog signals from the other pro-
vides the best performance. Connect the GND pin on the
MAX11158 to this ground plane. Keep the ground return to
the power supply low impedance and as short as possible
for noise-free operation.
A 4.7nF C0G (or NPO) ceramic chip capacitor should be
placed between AIN+ and the ground plane as close as
possible to the MAX11158. This capacitor reduces the
inductance seen by the sampling circuitry and reduces
the voltage transient seen by the input source circuit. If
AIN- is to be used for remote sense, put a matching 4.7nF
C0G ceramic capacitor as close to this pin as well to mini-
mize the effect to the inductance in the remote sense line.
For best performance, decouple the REF output to the
ground plane with a 16V, 10µF or larger ceramic chip
capacitor with a X5R or X7R dielectric in a 1210 or smaller
case size. Ensure that all bypass capacitors are connect-
ed directly into the ground plane with an independent via.
Bypass VDD and OVDD to the ground plane with 0.1FF
ceramic chip capacitors on each pin as close as pos-
sible to the device to minimize parasitic inductance.
Add at least one bulk 10FF decoupling capacitor to V_DD
and OVDD per PCB. For best performance, bring a
V_DD power plane in on the analog interface side of the
MAX11158 and a OVDD power plane from the digital
interface side of the device.
Definitions
Integral Nonlinearity
Integral nonlinearity (INL) is the deviation of the values on
an actual transfer function from a straight line. For these
devices, this straight line is a line drawn between the end
points of the transfer function, once offset and gain errors
have been nullified.
Differential Nonlinearity
Differential nonlinearity (DNL) is the difference between
an actual step width and the ideal value of 1 LSB. For
these devices, the DNL of each digital output code is
measured and the worst-case value is reported in the
Electrical Characteristics table. A DNL error specification
of less than ±1 LSB guarantees no missing codes and a
monotonic transfer function.
Offset Error
For the MAX11158, the offset error is defined at code
center 0x20000. This code center should occur at 0V
input between AIN+ and AIN-. The offset error is the
actual voltage required to produce code center 0x20000,
expressed in LSB.
Gain Error
Gain error is defined as the difference between the actual
change in analog input voltage range required to produce
a top code transition minus a bottom code transition,
subtracted from the ideal change in analog input voltage
range.
Signal-to-Noise Ratio
For a waveform perfectly reconstructed from digital
samples, signal-to-noise ratio (SNR) is the ratio of the full-
scale analog input power to the RMS quantization error
(residual error). The ideal, theoretical minimum analog-
to-digital noise is caused by quantization noise error only
and results directly from the ADC’s resolution (N bits):
SNR = (6.02 x N + 1.76)dB
In reality, there are other noise sources besides quantiza-
tion noise: thermal noise, reference noise, clock jitter, etc.
SNR is computed by taking the ratio of the power signal to
the power noise, which includes all spectral components
not including the fundamental, the first five harmonics,
and the DC offset.
Signal-to-Noise Plus Distortion
Signal-to-noise plus distortion (SINAD) is the ratio of the
fundamental input frequency’s power to the power of all
the other ADC output signals:
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