MAX16031 Datasheet, PDF (36/42 Pages) Maxim Integrated Products – EEPROM-Based System Monitors with Nonvolatile Fault Memory

EEPROM-Based System Monitors
with Nonvolatile Fault Memory
V_DBP
R_PU
TDI
TMS
TCK
REGISTERS
AND EEPROM
MEMORY WRITE REGISTER
[LENGTH = 8 BITS]
MEMORY READ REGISTER
[LENGTH = 8 BITS]
MEMORY ADDRESS REGISTER
[LENGTH = 8 BITS]
BOUNDARY SCAN REGISTER
[LENGTH = 198 BITS]
USER CODE REGISTER
[LENGTH = 32 BITS]
IDENTIFICATION REGISTER
[LENGTH = 32 BITS]
BYPASS REGISTER
[LENGTH = 1 BIT]
INSTRUCTION REGISTER
[LENGTH = 5 BITS]
TEST ACCESS PORT
(TAP) CONTROLLER
01101
01100
01010
01001
01000
MUX 1
00001
00010
00100
00000
11111
COMMAND
DECODER
01101
01100
SAVE
REBOOT
MUX 2
TDO
Figure 6. JTAG Block Diagram
Run-Test/Idle: The run-test/idle state is used between
scan operations or during specific tests. The instruction
register and test data registers remain idle.
Select-DR-Scan: All test data registers retain their pre-
vious state. With TMS low, a rising edge of TCK moves
the controller into the capture-DR state and initiates a
scan sequence. TMS high during a rising edge on TCK
moves the controller to the select-IR-scan state.
Capture-DR: Data are parallel-loaded into the test data
registers selected by the current instruction. If the instruc-
tion does not call for a parallel load or the selected test
data register does not allow parallel loads, the test data
register remains at its current value. On the rising edge of
TCK, the controller goes to the shift-DR state if TMS is low
or it goes to the exit1-DR state if TMS is high.
Shift-DR: The test data register selected by the current
instruction is connected between TDI and TDO and
shifts data one stage toward its serial output on each
rising edge of TCK while TMS is low. On the rising edge
of TCK, the controller goes to the exit1-DR state if TMS
is high.
Exit1-DR: While in this state, a rising edge on TCK puts
the controller in the update-DR state. A rising edge on
TCK with TMS low puts the controller in the pause-DR
state.
Pause-DR: Shifting of the test data registers is halted
while in this state. All test data registers retain their pre-
vious state. The controller remains in this state while
TMS is low. A rising edge on TCK with TMS high puts
the controller in the exit2-DR state.
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