MAX15569 Datasheet, PDF (36/41 Pages) Maxim Integrated Products – 2-Phase/1-Phase QuickTune-PWM Controller with Serial I2C Interface

MAX15569
2-Phase/1-Phase QuickTune-PWM Controller with
Serial I²C Interface
Input Capacitor Selection
The input capacitor must meet the ripple-current require-
ment (I_RMS) imposed by the switching currents. The
multiphase QuickTune-PWM controllers operate out-of
phase, reducing the RMS input. The I_RMS requirements
can be determined by the following equation:
( ) ^I_RMS ⁼



I_LOAD
N_PH × V_IN



N_PH × V_OUT V_IN - (N_PH × V_OUT)
The worst-case RMS current requirement occurs when
operating with V_IN = 2 (N_PH × V_OUT). Therefore, the
above equation simplifies to I_RMS = 0.5 x (I_LOAD/NPH).
Choose an input capacitor that exhibits less than 10°C
temperature rise at the RMS input current for optimal
circuit longevity.
Applications Information
PCB Layout Guidelines
Careful PCB layout is critical to achieve low switching
losses and clean, stable operation. The switching power
stage requires particular attention. If possible, mount
all the power components on the top side of the board,
with their ground terminals flush against one another.
The layout of the device is intimately related to the
layout of the CPU. The high-current output paths from the
regulator must flow cleanly into the high-current inputs
on the processor. For VR12.6 processors, these inputs
are orthogonal. This arrangement effectively forces the
regulator to be located diagonally, with respect to the
processor. Refer to the MAX15569 evaluation kit speci-
fications for layout examples and follow these guidelines
for good PCB layout:
● Keep the high-current paths short, especially at the
ground terminals. This is essential for stable, jitter-free
operation.
● Connect all analog grounds to a separate solid-
copper plane that connects to the ground pin of the
QuickTune-PWM controller. This includes the V_BIAS
bypass capacitor, FB, and GNDS bypass capacitors.
● Keep the power traces and load connections short.
This is essential for high efficiency. The use of thick
copper PCB (2oz vs. 1oz) can enhance full-load
efficiency by 1% or more. Correctly routing PCB traces
is a difficult task that must be approached in terms of
fractions of centimeters, where a single mΩ of excess
trace resistance causes a measurable efficiency
penalty.
● CSP_ and CSN_ connections for current limiting, load-
line control, and current monitoring must be made
using Kelvin-sense connections to guarantee the
current-sense accuracy.
● When trade-offs in trace lengths must be made, it is
preferable to allow the inductor charging path to be
made longer than the discharge path. For example,
it is better to allow some extra distance between the
input capacitors and the high-side MOSFET than to
allow distance between the inductor and the low-side
MOSFET, or between the inductor and the output filter
capacitor.
● Route high-speed switching nodes away from sensi-
tive analog areas (i.e., FB, FBAC, CSP_, CSN_, etc.).
See Table 12 for layout procedures.
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