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MAX15569 Datasheet, PDF (25/41 Pages) Maxim Integrated Products – 2-Phase/1-Phase QuickTune-PWM Controller with Serial I2C Interface
MAX15569
2-Phase/1-Phase QuickTune-PWM Controller with
Serial I2C Interface
Soft-start uses the slow slew rate, as set by the default
setting in the SRREG register, which is a fraction of the
fast slew rate. See the slew-rate accuracy specification in
the Electrical Characteristics section. The average induc-
tor current per phase that is required to make an output-
voltage transition is given by:
IL =
C OUT
NPH
×
dVTARGET
dt
where dVTARGET/dt is the required slew rate, COUT is
the total output capacitance, and NPH is the number of
active phases.
At the beginning of an output-voltage transition, the
device blanks the INT, so the open-drain output enters a
high-impedance state during output-voltage transitions.
The controller releases the INT output approximately
4µs (typ) after the slew-rate controller reaches the target
output voltage.
Automatic Pulse-Skipping Operation
The device automatically operates with a 2-phase pulse-
skipping control scheme. A logic-low level on DRVSKP
enables the zero-crossing comparator of the driver
(MAX17492) or power stage (MAX15515). Therefore,
these devices disable their low-side MOSFETs when they
detect “zero” inductor current. This keeps the inductor
from discharging the output capacitors and forces the
controller to skip pulses under light-load conditions to
avoid overcharging the output.
If the system changes the VID code to a lower voltage, the
device drives DRVSKP high to disable the pulse-skipping
mode. This allows the regulator to actively discharge the
output at the programmed slew rate.
To disable pulse-skipping mode so the regulator continu-
ally operates in forced-PWM operation, leave DRVSKP
unconnected and connect the pulse-skipping control input
on the driver or power stage to ground.
Automatic Pulse-Skipping Switchover
In pulse-skipping mode, an inherent automatic switchover
to PFM takes place at light loads. This switchover is affect-
ed by a comparator that truncates the low-side switch
on-time at the inductor current’s zero crossing. The zero-
crossing detection is designed into the MAX17492 driver
and the MAX15515 power stage. They sense the inductor
current across the low-side MOSFET. Once the LX volt-
age crosses the zero-crossing comparator threshold, the
low-side MOSFET turns off. This mechanism causes the
threshold between pulse-skipping PFM and non-skipping
PWM operation to coincide with the boundary between
continuous and discontinuous inductor-current operation.
The PFM/PWM crossover occurs when the load current of
each phase is equal to 1/2 the peak-to-peak ripple current
that is a function of the inductor value. Even for wide 4.5V
to 14V input voltage ranges, this crossover is relatively
constant, with only a minor dependence on the input volt-
age due to the typically low duty cycles. The total load cur-
rent at the PFM/PWM crossover threshold (ILOAD(SKIP))
is approximately:
ILOAD(SKIP)=
(VIN-VOUT ) t ON
2L
Power-Up Sequence (POR, UVLO)
Power-on reset (POR) occurs when VBIAS and VTT
rise above approximately 2V. POR resets the fault
latch and loads the default register settings. The VBIAS
UVLO circuitry inhibits switching until VBIAS rises
above 4.5V. The controller powers up the reference
once the system enables the controller, VBIAS is above
4.5V, and EN is driven high (see Figure 2). With the
reference in regulation, the controller ramps up to the
selected output voltage (register 0x07h) at the selected
slow slew rate (register 0x06h)
After this initialization, the PWM controller begins
switching:
t
TRAN(START)=
VBOOT
(dVTARGET
/dt)
where dVTARGET/dt is the slew rate. The soft-start slew
rate is the slow slew rate set by the default setting in the
SRREG register. The soft-start circuitry does not use a
variable current limit, so full output current is available
immediately.
Interrupt (INT)
The device provides an active-low interrupt output (INT)
to indicate that the startup sequence is complete and
the output voltage has moved to the programmed VID
value. This signal is intended for system monitoring of
the device. INT remains high impedance during normal
DC-DC operation. The controller asserts INT to alert the
system of an alarm event or if a fault condition occurs.
See the Alarms and Fault Protection (Latched) sections
for details (and Figure 7).
Use an external pullup resistor between INT and 3.3V to
deliver a valid logic-level output.
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