MAX15569 Datasheet, PDF (27/41 Pages) Maxim Integrated Products – 2-Phase/1-Phase QuickTune-PWM Controller with Serial I2C Interface

MAX15569
2-Phase/1-Phase QuickTune-PWM Controller with
Serial I²C Interface
Fault Protection (Latched)
TON Open-Circuit Protection
The TON input includes open-circuit protection to avoid
long, uncontrolled on-times that could result in an over-
voltage condition on the output. The device detects an
open-circuit fault if the TON current drops below 6µA
(typ) for any reason (e.g., the TON resistor (R_TON) is
unpopulated, a high-resistance value is used, the input
voltage is low, etc.). Under these conditions, the device
stops switching (DRVPWM_ outputs become high imped-
ance and DRVSKP is pulled low) and immediately sets
the fault latch.
Toggle EN or cycle power (BIAS) below 1V to clear the
fault latch and reactivate the controller. The TON open-
circuit fault is not indicated in the STATUS register.
Output Overvoltage Protection (OVP)
The OVP circuit is designed to protect the load against a
shorted high-side MOSFET by drawing high current and
activating the adapter or battery protection circuits. The
device continuously monitors the output for an overvolt-
age fault. An OVP fault is detected if the output voltage
exceeds the VID DAC voltage by more than 300mV (min),
or the fixed 1.83V (typ) threshold during a downward VID
transition in skip mode.
During pulse-skipping operation, the OVP threshold
tracks the VID DAC voltage as soon as the output is in
regulation; otherwise, the fixed 1.83V (typ) threshold is
used. When the OVP circuit detects an overvoltage fault,
the DRVPWM_ outputs become high impedance and the
DRVSKP output is pulled high. OVP is disabled in the
standby power state (EN pulled low).
After the fault condition occurs, the I²C interface remains
active so the STATUS register can be read to determine
what triggered the fault. Toggle EN or cycle power (BIAS)
below 1V to clear the fault latch. With the fault latch
cleared and the fault condition removed, the regulator
powers back up and the fault conditions are deasserted
in the STATUS register.
Output Undervoltage Protection (UVP)
If the output voltage is 200mV (min) below the target volt-
age and stays below this level for 200µs (typ), the con-
troller activates the shutdown sequence. The regulator
turns on a 2kΩ discharge resistor and sets the fault latch.
DRVPWM_ outputs go to the high-impedance mode and
DRVSKP is pulled low.
After the fault condition occurs, the I²C interface remains
active so the STATUS register can be read to determine
what triggered the fault. Toggle EN or cycle power (BIAS)
below 1V to clear the fault latch. With the fault latch
cleared and the fault condition removed, the regulator
powers back up and the fault conditions are deasserted
in the STATUS register.
Thermal-Fault Protection (TSHDN)
The device features an internal thermal-fault protec-
tion circuit. When the junction temperature rises above
+160°C, a thermal sensor sets the fault latch and
DRVPWM_ becomes high impedance.
After the fault condition occurs, the I²C interface remains
active so the STATUS register can be read to determine
what triggered the fault. Toggle EN or cycle power (BIAS)
below 1V to clear the fault latch. With the fault latch
cleared, the regulator powers back up and the fault condi-
tions are deasserted in the STATUS register, as long as
the regulator has cooled by 15°C (typ).
External Driver and Disabling Phases
The device supports an external driver (MAX15515) for
both phases. The DRVPWM_ outputs provide the signals
to trigger the drivers. Connecting CSP2 to BIAS of the
device disables the second phase.
The device provides a pulse-skipping-mode control output
(DRVSKP) for the external driver control. DRVSKP goes
high when the controller detects an output overvoltage-
fault condition. DRVSKP is high during output-voltage
transitions. The DRVSKP output is unconnected in shut-
down.
I²C Interface, Commands, Registers,
and Digital Control
A simplified register summery of the I²C interface for the
device is shown in Table 4. The I²C interface consists of
a high-speed transceiver capable of 3.4MHz data rate.
Regulator Address
The device does not feature programmable addressing.
These devices are hard-coded with bus address 70h.
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