MAX15569 Datasheet, PDF (10/41 Pages) Maxim Integrated Products – 2-Phase/1-Phase QuickTune-PWM Controller with Serial I2C Interface

MAX15569
2-Phase/1-Phase QuickTune-PWM Controller with
Serial I²C Interface
Pin Description (continued)
PIN
NAME
FUNCTION
Analog and Driver Supply Voltage Input. BIAS provides the supply voltage for the driver’s PWM
13
BIAS
and skip control outputs. Connect BIAS to the same supply used by the external drivers (typically
the 4.5V to 5.5V system supply voltage). Bypass BIAS to power ground with a local 1μF or
greater ceramic capacitor.
14
PGND
Power Ground
Direct-Drive PWM Output for Controlling the External First-Phase Driver. The DRVPWM1
15
DRVPWM1 push-pull output drives the signal between BIAS and PGND. DRVPWM1 is high impedance in
shutdown and after fault conditions (output overvoltage/undervoltage or thermal fault).
External Driver Skip-Mode Control Output. The DRVSKP output is low in standby. DRVSKP goes
high when the controller detects an output overvoltage fault condition, or during dynamic output-
16
DRVSKP
voltage transitions.
For applications operating with forced-PWM operation, disable the driver zero-crossing detection
and leave DRVSKP unconnected.
Direct-Drive PWM Output for Controlling the External Second-Phase Driver. The DRVPWM2
17
DRVPWM2 push-pull output drives the signal between BIAS and PGND. DRVPWM2 is high impedance in
shutdown and after fault conditions (output overvoltage, output undervoltage, or thermal fault).
Switching Frequency Adjustment Input. An external resistor between the input power source and
TON sets the switching period (per phase) according to the following equation:
18
TON
f_SW = (R_TON + 6.5kΩ) x 5pF
where f_SW = 1/f_SW is the nominal switching frequency. A 200kΩ resistor provides a typical
operating frequency of 1MHz.
TON is high impedance in shutdown.
Open-Drain Interrupt Output. INT is triggered by latched faults (output undervoltage, output
overvoltage, thermal shutdown), sticky alarms (internal overcurrent (OC), non-sticky alarms
(voltage regulator hot (VRHOT), and VID code violations (VOUTMAX)). The fault conditions and
alarms can be masked through register 0x05h. Masking these signals only prevents INT from
19
INT
being asserted; the STATUS register still asserts when any of these conditions occur.
INT remains high in standby mode (EN pulled low) to reduce power through the pullup resistor.
INT is pulled low during soft-start. After completing the soft-start sequence, INT becomes high
impedance as long as FB remains in regulation and there are no active alarms.
To obtain a logic signal, pull up INT with an external resistor connected to a logic supply.
Positive Current-Sense Input for the First Phase.
1) Connect CSP1 to the positive side of the current-sense resistor or the DCR sense filter
20
CSP1
capacitor of phase 1, as shown in Figure 4.
2) Connect CSP1 to the IOUT pin of the smart power stage (MAX15515). A resistor across
CSP1 and CSN1 sets the current-sense gain, as shown in Figure 3.
See the Current Sense section.
Negative Current-Sense Input for the First Phase. Connect CSN1 to the negative side of the
21
CSN1
current-sense element, as shown in Figure 4. An internal 2kΩ discharge MOSFET between CSN1
and ground is enabled under an input UVLO or shutdown condition.
22
N.C.
No Connection Internally
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