MAX15569 Datasheet, PDF (21/41 Pages) Maxim Integrated Products – 2-Phase/1-Phase QuickTune-PWM Controller with Serial I2C Interface

MAX15569
2-Phase/1-Phase QuickTune-PWM Controller with
Serial I²C Interface
Differential Output-Voltage Remote Sense
The device includes differential, remote-sense inputs
to eliminate the effects of voltage drops along the PCB
traces and through the power pins of the processor. The
feedback-sense node connects to the load-line resistor/
capacitor network (R_DROOP/C_FBAC). The ground-sense
(GNDS) input connects to an amplifier that adjusts the
feedback voltage to counteract the voltage drop in the
ground plane. Connect the load-line resistor (R_DROOP)
and ground-sense (GNDS) input directly to the remote-
sense outputs of the processor, as shown in Figure 6. The
correction range is bounded to less than ±200mV. The
remote-sense lines draw less than ±0.5µA to minimize
the offset errors.
Steady-State Integrator Amplifier
The device utilizes internal integrator amplifiers that force
the DC average of the FB voltage to equal the target
voltage, allowing accurate DC output-voltage regula-
tion regardless of the output voltage. The integrator is
designed to correct for the steady-state offsets/errors.
Nominal Output-Voltage Selection
The nominal no-load output voltage (V_TARGET) is defined
by the selected voltage reference, plus the remote
ground-sense adjustment (V_GNDS), as defined in the
following equation:
V_TARGET = V_FB - V_DAC + V_GNDS
where V_DAC is the selected output voltage.
On startup, the device slews the target voltage from
ground to the default 1V boot voltage unless a different
voltage code is selected before EN is pulled high.
Dynamic Output-Voltage Transitions
The device’s transition time depends on the slew-rate
setting, the selected SETVOUT voltage difference, and
the accuracy of the slew-rate controller (see the slew rate
section in the Electrical Characteristics section). The slew
rate is not dependent on the total output capacitance, as
long as the required transition current plus existing load
current remains below the current limit. For dynamic VID
transitions, the transition time (t_TRAN) is given by:
t _TRAN=
V_NEW - V_OLD
( ^dVTARGET )
dt
where dV_TARGET/dt is the slew rate (register 0x06h),
V_OLD is the original output voltage, and V_NEW is the new
target voltage (see Table 3).
Table 3. Output-Voltage Selection
LINE
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
BIT 7*
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
BIT 6
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BIT 5
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BIT 4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
BIT 3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
BIT 2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
BIT 1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
BIT 0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
HEX
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
VOLTAGE
0.000
0.500
0.510
0.520
0.530
0.540
0.550
0.560
0.570
0.580
0.590
0.600
0.610
0.620
0.630
0.640
0.650
0.660
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