MAX15569 Datasheet, PDF (35/41 Pages) Maxim Integrated Products – 2-Phase/1-Phase QuickTune-PWM Controller with Serial I2C Interface

MAX15569
2-Phase/1-Phase QuickTune-PWM Controller with
Serial I²C Interface
The actual capacitance value required relates to the
physical size needed to achieve low ESR, as well as to
the chemistry of the capacitor technology. The capacitor is
usually selected by ESR and voltage rating rather than by
capacitance value (this is true for polymer types). When
using low-capacity ceramic filter capacitors, capacitor size
is usually determined by the capacity needed to prevent
V_SAG and V_SOAR from causing problems during load
transients. Generally, once enough capacitance is added
to meet the overshoot requirement, undershoot at the
rising load edge is no longer a problem (see the V_SAG
and V_SOAR equations in the Transient Response section).
Output Capacitor Stability Considerations
For QuickTune-PWM controllers, stability is determined
by the value of the ESR zero relative to the switching
frequency. The boundary of instability is given by the
following equation:
f_ESR
≤
f_SW
π
where:
f_ESR
=
2π
×
1
R _EFF
×
C _OUT
and:
R_EFF= R_ESR + R_LL + R_PCB
where C_OUT is the total output capacitance, R_ESR is the
total equivalent series resistance, R_LL is the load-line
gain, and R_PCB is the parasitic board resistance between
the output capacitors and sense resistors. For a 1MHz
application, the ESR zero frequency must be well below
300kHz, preferably below 100kHz. SANYO POSCAP
and Panasonic SP capacitors are widely used and have
typical ESR zero frequencies below 100kHz.
Ceramic capacitors have a high-ESR zero frequency,
but applications with significant load-line (DC-coupled
or AC-coupled) can take advantage of their size and
low ESR. When using only ceramic output capacitors,
output overshoot (V_SOAR) typically determines the mini-
mum output-capacitance requirement. Their relatively
low capacitance value favors high-switching-frequency
operation with small inductor values to minimize the
energy transferred from inductor to capacitor during load-
step recovery. Unstable operation manifests itself in two
related but distinctly different ways: Double pulsing and
feedback-loop instability.
Double Pulsing and Feedback-Loop Instability
Double pulsing occurs due to noise on the output or
because the ESR is so low that there is not enough volt-
age ramp in the output-voltage signal. This “fools” the error
comparator into triggering a new cycle immediately after
the minimum off-time period has expired. Double pulsing
is more annoying than harmful, resulting in nothing worse
than increased output ripple. However, it can indicate the
possible presence of loop instability due to insufficient
ESR. Loop instability can result in oscillations at the out-
put after line or load steps. Such perturbations are usually
damped, but can cause the output voltage to rise above
or fall below the tolerance limits. The easiest method
for checking stability is to apply a very fast 10% to 90%
maximum load transient and carefully observe the output-
voltage ripple envelope for overshoot and ringing. It can
help to simultaneously monitor the inductor current with
an AC current probe. Do not allow more than one cycle
of ringing after the initial step-response under/overshoot.
Transient Response
The inductor-ripple current impacts transient-response
performance, especially at low V_IN - V_OUT differentials.
Low inductor values allow the inductor current to slew
faster, replenishing charge removed from the output filter
capacitors by a sudden load step. The amount of output
sag is also a function of the maximum duty factor, which
can be calculated from the on-time and minimum off-time.
For a multiphase controller, the worst-case output sag
voltage can be determined by:
V_SAG
≈
L( DI_LOAD(MAX) ) ²
2N_PH × C_OUT × V_OUT
×
t _MIN
t _SW - t_MIN
and:
t _M= _IN t _ON + t _OFF(MIN)
where t_OFF(MIN) is the minimum off-time (see the Electrical
Characteristics section), t_SW is the programmed switch-
ing period, and N_PH is the total number of active phases.
V_SAG must be less than the transient droop, ΔI_LOAD(MAX)
x R_LL. The capacitive soar voltage due to stored inductor
energy can be calculated as:
V_SOAR
≈
( DI_LOAD(MAX) ) ²L
2N_PH × C_OUT × V_OUT
The actual peak of the soar voltage depends on the time
where the decaying ESR step and rising capacitive soar
are at their maximum. This is best simulated or measured.
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