MAX1385 Datasheet, PDF (30/52 Pages) Maxim Integrated Products – Dual RF LDMOS Bias Controllers with I2C/SPI Interface

Dual RF LDMOS Bias Controllers
with I²C/SPI Interface
Table 7. DCFIG (Read/Write)
Table 7a. Gain-Setting Modes
BIT NAME
X
PG2SET1
PG2SET0
PG1SET1
PG1SET0
CKSEL1
CKSEL0
REFADC1
REFADC0
REFDAC1
REFDAC0
DATA BIT
D15–D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
POR
FUNCTION
X Don’t care
0 PGA 2 gain-setting
0 PGA 2 gain-setting
0 PGA 1 gain-setting
0 PGA 1 gain-setting
0
Clock mode and CNVST
configuration
0
Clock mode and CNVST
configuration
0 ADC reference select
0 ADC reference select
0 DAC reference select
0 DAC reference select
Alarm Modes section). Setting ALARMCMP does not
affect SAFE1 and SAFE2 outputs. Program
ALARMHYST1 and ALARMHYST0 to set the amount of
built-in hysteresis used in window-threshold mode.
See the ALARM Output and SAFE1/SAFE2 Outputs
sections for a description of the relationship between
ALARM and SAFE1 and SAFE2. Set TALARM2 to 1 to
allow channel 2 temperature measurements to control
the state of SAFE2 and ALARM based on channel 2
temperature thresholds. Set TWIN2 to 0 to enable hys-
teresis-threshold mode and to 1 to enable window-
threshold mode for channel 2 temperature
measurements (see the Alarm Modes section). Set
IALARM2 to 1 to allow channel 2 current measurements
to control the state of SAFE2 and ALARM based on
channel 2 current thresholds. Set IWIN2 to 0 to enable
hysteresis-threshold mode and to 1 to enable window-
threshold mode for channel 2 current measurements.
Set TALARM1 to 1 to allow channel 1 temperature mea-
surements to control the state of SAFE1 and ALARM
based on channel 1 temperature thresholds. Set TWIN1
to 0 to enable hysteresis-threshold mode and to 1 to
enable window-threshold mode for channel 1 tempera-
ture measurements (see the Alarm Modes section). Set
IALARM1 to 1 to allow channel 1 current measurements
to control the state of SAFE1 and ALARM based on
channel 1 current thresholds. Set IWIN1 to 0 to enable
hysteresis-threshold mode and to 1 to enable window-
threshold mode for channel 1 current measurements.
HIWIPE1 and HIWIPE2 (Read/Write)
Write to the Coarse DAC1/DAC2 High Wiper Input reg-
ister by sending the appropriate write command byte
PG_SET1 PG_SET0
0
0
0
1
1
X
X = Don’t care.
FUNCTION
PGA_ gain of 2
PGA_ gain of 10
PGA_ gain of 25
Table 7b. Clock Modes
CKSEL1
CKSEL0
CONVERSION
CLOCK
ACQUISITION/
SAMPLING
Internally timed
acquisitions and
conversions.
0
0
Internal
Conversions started by
a write to the Analog-
to-Digital Conversion
register or setting the
CONCONV bit.
Internally timed
acquisitions and
0
1
Internal
conversions.
Conversions begin with
a high-to-low transition
at CNVST.
1
0
—
Reserved. Do not use.
Externally timed
1
1
Internal
acquisitions by
CNVST. Conversions
internally timed.
Table 7c. ADC Reference Selection
REFADC1 REFADC0
DESCRIPTION
0
X
External. Bypass REFADC with a
0.1µF capacitor to AGND.
1
0
Internal. Leave REFADC
unconnected.
Internal. Connect a 0.1µF capacitor
1
1
to REFADC for better noise
performance.
X = Don’t care.
followed by data bits D15–D0 (see Table 9). Bits
D14–D8 are don’t care. Read the Coarse DAC1/DAC2
High Wiper Input register by sending the appropriate
read command byte. The DAC output is not updated
until an LDAC command is issued, at which point the
30 ______________________________________________________________________________________