MAX1280 Datasheet, PDF (20/24 Pages) Maxim Integrated Products – 400ksps/300ksps, Single-Supply, Low-Power, 8-Channel, Serial 12-Bit ADCs with Internal Reference

400ksps/300ksps, Single-Supply, Low-Power, 8-Channel,
Serial 12-Bit ADCs with Internal Reference
Table 5. Full Scale and Zero Scale
UNIPOLAR MODE
Full Scale
Zero Scale
V_REF + V_COM
COM
Positive
Full Scale
VREF / 2
+ V_COM
BIPOLAR MODE
Zero
Scale
V_COM
Negative
Full Scale
-VREF / 2
+ V_COM
SUPPLIES
V_DD1
GND
V_DD2
R* = 10Ω
V_DD1
GND
COM V_DD2
V_DD DGND
MAX1280
MAX1281
DIGITAL
CIRCUITRY
*OPTIONAL
Figure 16. Power-Supply Grounding Connection
High-Speed Digital Interfacing with QSPI
The MAX1280/MAX1281 can interface with QSPI using
the circuit in Figure 17 (f_SCLK = 4.0MHz, CPOL = 0,
CPHA = 0). This QSPI circuit can be programmed to do
a conversion on each of the eight channels. The result
is stored in memory without taxing the CPU, since QSPI
incorporates its own microsequencer.
TMS320LC3x Interface
Figure 18 shows an application circuit that interfaces
the MAX1280/MAX1281 to the TMS320 in external clock
mode. The timing diagram for this interface circuit is
shown in Figure 19.
Use the following steps to initiate a conversion in the
MAX1280/MAX1281 and to read the results:
1) The TMS320 should be configured with CLKX (trans-
mit clock) as an active-high output clock and with
CLKR (TMS320 receive clock) as an active-high
input clock. CLKX and CLKR on the TMS320 are
connected with the MAX1280/MAX1281’s SCLK
input.
2) The MAX1280/MAX1281’s CS pin is driven low by
the TMS320’s XF_ I/O port to enable data to be
clocked into the MAX1280/MAX1281’s DIN pin.
3) An 8-bit word (1XXXXX11) should be written to the
MAX1280/MAX1281 to initiate a conversion and
place the device into normal operating mode. See
Table 1 to select the proper XXXXX bit values for
your specific application.
4) The MAX1280/MAX1281’s SSTRB output is moni-
tored through the TMS320’s FSR input. A falling
edge on the SSTRB output indicates that the conver-
sion is in progress and data is ready to be received
from the MAX1280/MAX1281.
5) The TMS320 reads in one data bit on each of the
next 16 rising edges of SCLK. These data bits repre-
sent the 12-bit conversion result followed by four
trailing bits, which should be ignored.
6) Pull CS high to disable the MAX1280/MAX1281 until
the next conversion is initiated.
Definitions
Integral Nonlinearity
Integral nonlinearity (INL) is the deviation of the values
on an actual transfer function from a straight line. This
straight line can be either a best-straight-line fit or a line
drawn between the endpoints of the transfer function,
once offset and gain errors have been nullified. The
static linearity parameters for the MAX1280/MAX1281
are measured using the endpoint method.
Differential Nonlinearity
Differential nonlinearity (DNL) is the difference between
an actual step width and the ideal value of 1LSB. A
DNL error specification of less than 1LSB guarantees
no missing codes and a monotonic transfer function.
Aperture Jitter
Aperture jitter (t_AJ) is the sample-to-sample variation in
the time between the samples.
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