MAX1280 Datasheet, PDF (10/24 Pages) Maxim Integrated Products – 400ksps/300ksps, Single-Supply, Low-Power, 8-Channel, Serial 12-Bit ADCs with Internal Reference

400ksps/300ksps, Single-Supply, Low-Power, 8-Channel,
Serial 12-Bit ADCs with Internal Reference
Pin Description
PIN
NAME
FUNCTION
1–8
CH0–CH7 Sampling Analog Inputs
9
COM
Ground Reference for Analog Inputs. COM sets zero-code voltage in single-ended mode. Must be
stable to ±0.5LSB.
10
SHDN
Active-Low Shutdown Input. Pulling SHDN low shuts down the device, reducing supply current to 2µA
(typ).
Reference-Buffer Output/ADC Reference Input. Reference voltage for analog-to-digital conversion.
11
REF
In internal reference mode, the reference buffer provides a +2.500V nominal output, externally
adjustable at REFADJ. In external reference mode, disable the internal buffer by pulling REFADJ to
V_DD1.
12
REFADJ
Input to the Reference-Buffer Amplifier. To disable the reference-buffer amplifier, tie REFADJ to V_DD1.
13
GND
Analog and Digital Ground
14
DOUT
Serial Data Output. Data is clocked out at SCLK’s rising edge. High impedance when CS is high.
15
SSTRB
Serial Strobe Output. SSTRB pulses high for one clock period before the MSB decision. High imped-
ance when CS is high.
16
DIN
Serial Data Input. Data is clocked in at SCLK’s rising edge.
17
CS
Active-Low Chip Select. Data will not be clocked into DIN unless CS is low. When CS is high, DOUT
and SSTRB are high impedance.
18
SCLK
Serial Clock Input. Clocks data in and out of the serial interface and sets the conversion speed. (Duty
cycle must be 40% to 60%.)
19
V_DD2
Positive Supply Voltage
20
V_DD1
Positive Supply Voltage
V_DD2
DOUT
6k
DOUT
6k
GND
C_LOAD
20pF
C_LOAD
20pF
GND
a) High-Z to V_OH and V_OL to V_OH
b) High-Z to V_OL and V_OH to V_OL
Figure 1. Load Circuits for Enable Time
DOUT
6k
GND
V_DD2
6k
DOUT
C_LOAD
20pF
C_LOAD
20pF
GND
a) V_OH to High-Z
b) V_OL to High-Z
Figure 2. Load Circuits for Disable Time
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